2 * Copyright (c) 2004-2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 // Current ordering allows for 0 cycle added-to-scheduled. Could maybe fake
33 // it; either do in reverse order, or have added instructions put into a
34 // different ready queue that, in scheduleRreadyInsts(), gets put onto the
35 // normal ready queue. This would however give only a one cycle delay,
36 // but probably is more flexible to actually add in a delay parameter than
37 // just running it backwards.
41 #include "sim/core.hh"
43 #include "cpu/ozone/inst_queue.hh"
46 InstQueue<Impl>::FUCompletion::FUCompletion(DynInstPtr &_inst,
48 InstQueue<Impl> *iq_ptr)
49 : Event(&mainEventQueue, Stat_Event_Pri),
50 inst(_inst), fuIdx(fu_idx), iqPtr(iq_ptr)
52 this->setFlags(Event::AutoDelete);
57 InstQueue<Impl>::FUCompletion::process()
59 iqPtr->processFUCompletion(inst, fuIdx);
65 InstQueue<Impl>::FUCompletion::description()
67 return "Functional unit completion event";
71 InstQueue<Impl>::InstQueue(Params *params)
72 : dcacheInterface(params->dcacheInterface),
73 // fuPool(params->fuPool),
74 numEntries(params->numIQEntries),
75 totalWidth(params->issueWidth),
76 // numPhysIntRegs(params->numPhysIntRegs),
77 // numPhysFloatRegs(params->numPhysFloatRegs),
78 commitToIEWDelay(params->commitToIEWDelay)
82 // numThreads = params->numberOfThreads;
85 //Initialize thread IQ counts
86 for (int i = 0; i <numThreads; i++) {
90 // Initialize the number of free IQ entries.
91 freeEntries = numEntries;
93 // Set the number of physical registers as the number of int + float
94 // numPhysRegs = numPhysIntRegs + numPhysFloatRegs;
96 // DPRINTF(IQ, "There are %i physical registers.\n", numPhysRegs);
98 //Create an entry for each physical register within the
100 // dependGraph = new DependencyEntry[numPhysRegs];
102 // Resize the register scoreboard.
103 // regScoreboard.resize(numPhysRegs);
105 //Initialize Mem Dependence Units
106 for (int i = 0; i < numThreads; i++) {
107 memDepUnit[i].init(params,i);
108 memDepUnit[i].setIQ(this);
111 // Initialize all the head pointers to point to NULL, and all the
112 // entries as unready.
113 // Note that in actuality, the registers corresponding to the logical
114 // registers start off as ready. However this doesn't matter for the
115 // IQ as the instruction should have been correctly told if those
116 // registers are ready in rename. Thus it can all be initialized as
118 for (int i = 0; i < numPhysRegs; ++i) {
119 dependGraph[i].next = NULL;
120 dependGraph[i].inst = NULL;
121 regScoreboard[i] = false;
124 for (int i = 0; i < numThreads; ++i) {
125 squashedSeqNum[i] = 0;
128 for (int i = 0; i < Num_OpClasses; ++i) {
129 queueOnList[i] = false;
130 readyIt[i] = listOrder.end();
133 string policy = params->smtIQPolicy;
135 //Convert string to lowercase
136 std::transform(policy.begin(), policy.end(), policy.begin(),
137 (int(*)(int)) tolower);
139 //Figure out resource sharing policy
140 if (policy == "dynamic") {
143 //Set Max Entries to Total ROB Capacity
144 for (int i = 0; i < numThreads; i++) {
145 maxEntries[i] = numEntries;
148 } else if (policy == "partitioned") {
149 iqPolicy = Partitioned;
151 //@todo:make work if part_amt doesnt divide evenly.
152 int part_amt = numEntries / numThreads;
154 //Divide ROB up evenly
155 for (int i = 0; i < numThreads; i++) {
156 maxEntries[i] = part_amt;
159 DPRINTF(Fetch, "IQ sharing policy set to Partitioned:"
160 "%i entries per thread.\n",part_amt);
162 } else if (policy == "threshold") {
163 iqPolicy = Threshold;
165 double threshold = (double)params->smtIQThreshold / 100;
167 int thresholdIQ = (int)((double)threshold * numEntries);
169 //Divide up by threshold amount
170 for (int i = 0; i < numThreads; i++) {
171 maxEntries[i] = thresholdIQ;
174 DPRINTF(Fetch, "IQ sharing policy set to Threshold:"
175 "%i entries per thread.\n",thresholdIQ);
177 assert(0 && "Invalid IQ Sharing Policy.Options Are:{Dynamic,"
178 "Partitioned, Threshold}");
183 template <class Impl>
184 InstQueue<Impl>::~InstQueue()
186 // Clear the dependency graph
188 DependencyEntry *curr;
189 DependencyEntry *prev;
191 for (int i = 0; i < numPhysRegs; ++i) {
192 curr = dependGraph[i].next;
195 DependencyEntry::mem_alloc_counter--;
204 if (dependGraph[i].inst) {
205 dependGraph[i].inst = NULL;
208 dependGraph[i].next = NULL;
211 assert(DependencyEntry::mem_alloc_counter == 0);
213 delete [] dependGraph;
217 template <class Impl>
219 InstQueue<Impl>::name() const
221 return cpu->name() + ".iq";
224 template <class Impl>
226 InstQueue<Impl>::regStats()
229 .name(name() + ".iqInstsAdded")
230 .desc("Number of instructions added to the IQ (excludes non-spec)")
231 .prereq(iqInstsAdded);
234 .name(name() + ".iqNonSpecInstsAdded")
235 .desc("Number of non-speculative instructions added to the IQ")
236 .prereq(iqNonSpecInstsAdded);
241 .name(name() + ".iqIntInstsIssued")
242 .desc("Number of integer instructions issued")
243 .prereq(iqIntInstsIssued);
245 // iqFloatInstsAdded;
248 .name(name() + ".iqFloatInstsIssued")
249 .desc("Number of float instructions issued")
250 .prereq(iqFloatInstsIssued);
252 // iqBranchInstsAdded;
255 .name(name() + ".iqBranchInstsIssued")
256 .desc("Number of branch instructions issued")
257 .prereq(iqBranchInstsIssued);
262 .name(name() + ".iqMemInstsIssued")
263 .desc("Number of memory instructions issued")
264 .prereq(iqMemInstsIssued);
269 .name(name() + ".iqMiscInstsIssued")
270 .desc("Number of miscellaneous instructions issued")
271 .prereq(iqMiscInstsIssued);
273 iqSquashedInstsIssued
274 .name(name() + ".iqSquashedInstsIssued")
275 .desc("Number of squashed instructions issued")
276 .prereq(iqSquashedInstsIssued);
278 iqSquashedInstsExamined
279 .name(name() + ".iqSquashedInstsExamined")
280 .desc("Number of squashed instructions iterated over during squash;"
281 " mainly for profiling")
282 .prereq(iqSquashedInstsExamined);
284 iqSquashedOperandsExamined
285 .name(name() + ".iqSquashedOperandsExamined")
286 .desc("Number of squashed operands that are examined and possibly "
287 "removed from graph")
288 .prereq(iqSquashedOperandsExamined);
290 iqSquashedNonSpecRemoved
291 .name(name() + ".iqSquashedNonSpecRemoved")
292 .desc("Number of squashed non-spec instructions that were removed")
293 .prereq(iqSquashedNonSpecRemoved);
295 for ( int i=0; i < numThreads; i++) {
296 // Tell mem dependence unit to reg stats as well.
297 memDepUnit[i].regStats();
302 template <class Impl>
304 InstQueue<Impl>::setActiveThreads(list<unsigned> *at_ptr)
306 DPRINTF(IQ, "Setting active threads list pointer.\n");
307 activeThreads = at_ptr;
310 template <class Impl>
312 InstQueue<Impl>::setIssueToExecuteQueue(TimeBuffer<IssueStruct> *i2e_ptr)
314 DPRINTF(IQ, "Set the issue to execute queue.\n");
315 issueToExecuteQueue = i2e_ptr;
318 template <class Impl>
320 InstQueue<Impl>::setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr)
322 DPRINTF(IQ, "Set the time buffer.\n");
325 fromCommit = timeBuffer->getWire(-commitToIEWDelay);
328 template <class Impl>
330 InstQueue<Impl>::entryAmount(int num_threads)
332 if (iqPolicy == Partitioned) {
333 return numEntries / num_threads;
340 template <class Impl>
342 InstQueue<Impl>::resetEntries()
344 if (iqPolicy != Dynamic || numThreads > 1) {
345 int active_threads = activeThreads->size();
347 std::list<unsigned>::iterator threads = activeThreads->begin();
348 std::list<unsigned>::iterator end = activeThreads->end();
350 while (threads != end) {
351 unsigned tid = *threads++;
353 if (iqPolicy == Partitioned) {
354 maxEntries[tid] = numEntries / active_threads;
355 } else if (iqPolicy == Threshold && active_threads == 1) {
356 maxEntries[tid] = numEntries;
362 template <class Impl>
364 InstQueue<Impl>::numFreeEntries()
369 template <class Impl>
371 InstQueue<Impl>::numFreeEntries(unsigned tid)
373 return maxEntries[tid] - count[tid];
376 // Might want to do something more complex if it knows how many instructions
377 // will be issued this cycle.
378 template <class Impl>
380 InstQueue<Impl>::isFull()
382 if (freeEntries == 0) {
389 template <class Impl>
391 InstQueue<Impl>::isFull(unsigned tid)
393 if (numFreeEntries(tid) == 0) {
400 template <class Impl>
402 InstQueue<Impl>::hasReadyInsts()
405 if (!listOrder.empty()) {
409 for (int i = 0; i < Num_OpClasses; ++i) {
410 if (!readyInsts[i].empty()) {
417 return readyInsts.empty();
420 template <class Impl>
422 InstQueue<Impl>::insert(DynInstPtr &new_inst)
424 // Make sure the instruction is valid
427 DPRINTF(IQ, "Adding instruction PC %#x to the IQ.\n",
430 // Check if there are any free entries. Panic if there are none.
431 // Might want to have this return a fault in the future instead of
433 assert(freeEntries != 0);
435 instList[new_inst->threadNumber].push_back(new_inst);
437 // Decrease the number of free entries.
440 //Mark Instruction as in IQ
441 // new_inst->setInIQ();
443 // Look through its source registers (physical regs), and mark any
445 addToDependents(new_inst);
447 // Have this instruction set itself as the producer of its destination
449 createDependency(new_inst);
451 // If it's a memory instruction, add it to the memory dependency
453 // if (new_inst->isMemRef()) {
454 // memDepUnit[new_inst->threadNumber].insert(new_inst);
456 // If the instruction is ready then add it to the ready list.
457 addIfReady(new_inst);
463 //Update Thread IQ Count
464 count[new_inst->threadNumber]++;
466 assert(freeEntries == (numEntries - countInsts()));
469 template <class Impl>
471 InstQueue<Impl>::insertNonSpec(DynInstPtr &new_inst)
473 nonSpecInsts[new_inst->seqNum] = new_inst;
475 // @todo: Clean up this code; can do it by setting inst as unable
476 // to issue, then calling normal insert on the inst.
478 // Make sure the instruction is valid
481 DPRINTF(IQ, "Adding instruction PC %#x to the IQ.\n",
484 // Check if there are any free entries. Panic if there are none.
485 // Might want to have this return a fault in the future instead of
487 assert(freeEntries != 0);
489 instList[new_inst->threadNumber].push_back(new_inst);
491 // Decrease the number of free entries.
494 //Mark Instruction as in IQ
495 // new_inst->setInIQ();
497 // Have this instruction set itself as the producer of its destination
499 createDependency(new_inst);
501 // If it's a memory instruction, add it to the memory dependency
503 if (new_inst->isMemRef()) {
504 memDepUnit[new_inst->threadNumber].insertNonSpec(new_inst);
507 ++iqNonSpecInstsAdded;
509 //Update Thread IQ Count
510 count[new_inst->threadNumber]++;
512 assert(freeEntries == (numEntries - countInsts()));
515 template <class Impl>
517 InstQueue<Impl>::advanceTail(DynInstPtr &inst)
519 // Have this instruction set itself as the producer of its destination
521 createDependency(inst);
524 template <class Impl>
526 InstQueue<Impl>::addToOrderList(OpClass op_class)
528 assert(!readyInsts[op_class].empty());
530 ListOrderEntry queue_entry;
532 queue_entry.queueType = op_class;
534 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
536 ListOrderIt list_it = listOrder.begin();
537 ListOrderIt list_end_it = listOrder.end();
539 while (list_it != list_end_it) {
540 if ((*list_it).oldestInst > queue_entry.oldestInst) {
547 readyIt[op_class] = listOrder.insert(list_it, queue_entry);
548 queueOnList[op_class] = true;
551 template <class Impl>
553 InstQueue<Impl>::moveToYoungerInst(ListOrderIt list_order_it)
555 // Get iterator of next item on the list
556 // Delete the original iterator
557 // Determine if the next item is either the end of the list or younger
558 // than the new instruction. If so, then add in a new iterator right here.
559 // If not, then move along.
560 ListOrderEntry queue_entry;
561 OpClass op_class = (*list_order_it).queueType;
562 ListOrderIt next_it = list_order_it;
566 queue_entry.queueType = op_class;
567 queue_entry.oldestInst = readyInsts[op_class].top()->seqNum;
569 while (next_it != listOrder.end() &&
570 (*next_it).oldestInst < queue_entry.oldestInst) {
574 readyIt[op_class] = listOrder.insert(next_it, queue_entry);
577 template <class Impl>
579 InstQueue<Impl>::processFUCompletion(DynInstPtr &inst, int fu_idx)
581 // The CPU could have been sleeping until this op completed (*extremely*
582 // long latency op). Wake it if it was. This may be overkill.
585 fuPool->freeUnit(fu_idx);
587 int &size = issueToExecuteQueue->access(0)->size;
589 issueToExecuteQueue->access(0)->insts[size++] = inst;
592 // @todo: Figure out a better way to remove the squashed items from the
593 // lists. Checking the top item of each list to see if it's squashed
594 // wastes time and forces jumps.
595 template <class Impl>
597 InstQueue<Impl>::scheduleReadyInsts()
599 DPRINTF(IQ, "Attempting to schedule ready instructions from "
602 // IssueStruct *i2e_info = issueToExecuteQueue->access(0);
604 // Will need to reorder the list if either a queue is not on the list,
605 // or it has an older instruction than last time.
606 for (int i = 0; i < Num_OpClasses; ++i) {
607 if (!readyInsts[i].empty()) {
608 if (!queueOnList[i]) {
609 addToOrderList(OpClass(i));
610 } else if (readyInsts[i].top()->seqNum <
611 (*readyIt[i]).oldestInst) {
612 listOrder.erase(readyIt[i]);
613 addToOrderList(OpClass(i));
618 // Have iterator to head of the list
619 // While I haven't exceeded bandwidth or reached the end of the list,
620 // Try to get a FU that can do what this op needs.
621 // If successful, change the oldestInst to the new top of the list, put
622 // the queue in the proper place in the list.
623 // Increment the iterator.
624 // This will avoid trying to schedule a certain op class if there are no
625 // FUs that handle it.
626 ListOrderIt order_it = listOrder.begin();
627 ListOrderIt order_end_it = listOrder.end();
628 int total_issued = 0;
629 int exec_queue_slot = i2e_info->size;
631 while (exec_queue_slot < totalWidth && order_it != order_end_it) {
632 OpClass op_class = (*order_it).queueType;
634 assert(!readyInsts[op_class].empty());
636 DynInstPtr issuing_inst = readyInsts[op_class].top();
638 assert(issuing_inst->seqNum == (*order_it).oldestInst);
640 if (issuing_inst->isSquashed()) {
641 readyInsts[op_class].pop();
643 if (!readyInsts[op_class].empty()) {
644 moveToYoungerInst(order_it);
646 readyIt[op_class] = listOrder.end();
647 queueOnList[op_class] = false;
650 listOrder.erase(order_it++);
652 ++iqSquashedInstsIssued;
657 int idx = fuPool->getUnit(op_class);
660 int op_latency = fuPool->getOpLatency(op_class);
662 if (op_latency == 1) {
663 i2e_info->insts[exec_queue_slot++] = issuing_inst;
666 // Add the FU onto the list of FU's to be freed next cycle.
667 fuPool->freeUnit(idx);
669 int issue_latency = fuPool->getIssueLatency(op_class);
671 if (issue_latency > 1) {
672 // Generate completion event for the FU
673 FUCompletion *execution = new FUCompletion(issuing_inst,
676 execution->schedule(curTick + issue_latency - 1);
678 i2e_info->insts[exec_queue_slot++] = issuing_inst;
681 // Add the FU onto the list of FU's to be freed next cycle.
682 fuPool->freeUnit(idx);
686 DPRINTF(IQ, "Thread %i: Issuing instruction PC %#x "
688 issuing_inst->threadNumber, issuing_inst->readPC(),
689 issuing_inst->seqNum);
691 readyInsts[op_class].pop();
693 if (!readyInsts[op_class].empty()) {
694 moveToYoungerInst(order_it);
696 readyIt[op_class] = listOrder.end();
697 queueOnList[op_class] = false;
700 issuing_inst->setIssued();
703 if (!issuing_inst->isMemRef()) {
704 // Memory instructions can not be freed from the IQ until they
707 count[issuing_inst->threadNumber]--;
708 issuing_inst->removeInIQ();
710 memDepUnit[issuing_inst->threadNumber].issue(issuing_inst);
713 listOrder.erase(order_it++);
720 cpu->activityThisCycle();
722 DPRINTF(IQ, "Not able to schedule any instructions.\n");
727 template <class Impl>
729 InstQueue<Impl>::scheduleNonSpec(const InstSeqNum &inst)
731 DPRINTF(IQ, "Marking nonspeculative instruction with sequence "
732 "number %i as ready to execute.\n", inst);
734 NonSpecMapIt inst_it = nonSpecInsts.find(inst);
736 assert(inst_it != nonSpecInsts.end());
738 // unsigned tid = (*inst_it).second->threadNumber;
740 // Mark this instruction as ready to issue.
741 (*inst_it).second->setCanIssue();
743 // Now schedule the instruction.
744 // if (!(*inst_it).second->isMemRef()) {
745 addIfReady((*inst_it).second);
747 // memDepUnit[tid].nonSpecInstReady((*inst_it).second);
750 nonSpecInsts.erase(inst_it);
753 template <class Impl>
755 InstQueue<Impl>::commit(const InstSeqNum &inst, unsigned tid)
757 /*Need to go through each thread??*/
758 DPRINTF(IQ, "[tid:%i]: Committing instructions older than [sn:%i]\n",
761 ListIt iq_it = instList[tid].begin();
763 while (iq_it != instList[tid].end() &&
764 (*iq_it)->seqNum <= inst) {
766 instList[tid].pop_front();
769 assert(freeEntries == (numEntries - countInsts()));
772 template <class Impl>
774 InstQueue<Impl>::wakeDependents(DynInstPtr &completed_inst)
776 DPRINTF(IQ, "Waking dependents of completed instruction.\n");
777 // Look at the physical destination register of the DynInst
778 // and look it up on the dependency graph. Then mark as ready
779 // any instructions within the instruction queue.
781 DependencyEntry *curr;
782 DependencyEntry *prev;
784 // Tell the memory dependence unit to wake any dependents on this
785 // instruction if it is a memory instruction. Also complete the memory
786 // instruction at this point since we know it executed fine.
787 // @todo: Might want to rename "completeMemInst" to
788 // something that indicates that it won't need to be replayed, and call
789 // this earlier. Might not be a big deal.
790 if (completed_inst->isMemRef()) {
791 // memDepUnit[completed_inst->threadNumber].wakeDependents(completed_inst);
792 completeMemInst(completed_inst);
794 completed_inst->wakeDependents();
796 for (int dest_reg_idx = 0;
797 dest_reg_idx < completed_inst->numDestRegs();
800 PhysRegIndex dest_reg =
801 completed_inst->renamedDestRegIdx(dest_reg_idx);
803 // Special case of uniq or control registers. They are not
804 // handled by the IQ and thus have no dependency graph entry.
805 // @todo Figure out a cleaner way to handle this.
806 if (dest_reg >= numPhysRegs) {
810 DPRINTF(IQ, "Waking any dependents on register %i.\n",
813 //Maybe abstract this part into a function.
814 //Go through the dependency chain, marking the registers as ready
815 //within the waiting instructions.
817 curr = dependGraph[dest_reg].next;
820 DPRINTF(IQ, "Waking up a dependent instruction, PC%#x.\n",
821 curr->inst->readPC());
823 // Might want to give more information to the instruction
824 // so that it knows which of its source registers is ready.
825 // However that would mean that the dependency graph entries
826 // would need to hold the src_reg_idx.
827 curr->inst->markSrcRegReady();
829 addIfReady(curr->inst);
831 DependencyEntry::mem_alloc_counter--;
840 // Reset the head node now that all of its dependents have been woken
842 dependGraph[dest_reg].next = NULL;
843 dependGraph[dest_reg].inst = NULL;
845 // Mark the scoreboard as having that register ready.
846 regScoreboard[dest_reg] = true;
851 template <class Impl>
853 InstQueue<Impl>::addReadyMemInst(DynInstPtr &ready_inst)
855 // OpClass op_class = ready_inst->opClass();
857 readyInsts.push(ready_inst);
859 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
860 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
861 ready_inst->readPC(), ready_inst->opClass(), ready_inst->seqNum);
864 template <class Impl>
866 InstQueue<Impl>::rescheduleMemInst(DynInstPtr &resched_inst)
868 memDepUnit[resched_inst->threadNumber].reschedule(resched_inst);
871 template <class Impl>
873 InstQueue<Impl>::replayMemInst(DynInstPtr &replay_inst)
875 memDepUnit[replay_inst->threadNumber].replay(replay_inst);
878 template <class Impl>
880 InstQueue<Impl>::completeMemInst(DynInstPtr &completed_inst)
882 int tid = completed_inst->threadNumber;
884 DPRINTF(IQ, "Completing mem instruction PC:%#x [sn:%lli]\n",
885 completed_inst->readPC(), completed_inst->seqNum);
889 // completed_inst->memOpDone = true;
891 // memDepUnit[tid].completed(completed_inst);
896 template <class Impl>
898 InstQueue<Impl>::violation(DynInstPtr &store,
899 DynInstPtr &faulting_load)
901 memDepUnit[store->threadNumber].violation(store, faulting_load);
904 template <class Impl>
906 InstQueue<Impl>::squash(unsigned tid)
908 DPRINTF(IQ, "[tid:%i]: Starting to squash instructions in "
911 // Read instruction sequence number of last instruction out of the
913 // squashedSeqNum[tid] = fromCommit->commitInfo[tid].doneSeqNum;
915 // Setup the squash iterator to point to the tail.
916 squashIt[tid] = instList[tid].end();
919 // Call doSquash if there are insts in the IQ
920 if (count[tid] > 0) {
924 // Also tell the memory dependence unit to squash.
925 // memDepUnit[tid].squash(squashedSeqNum[tid], tid);
928 template <class Impl>
930 InstQueue<Impl>::doSquash(unsigned tid)
932 // Make sure the squashed sequence number is valid.
933 assert(squashedSeqNum[tid] != 0);
935 DPRINTF(IQ, "[tid:%i]: Squashing until sequence number %i!\n",
936 tid, squashedSeqNum[tid]);
938 // Squash any instructions younger than the squashed sequence number
940 while (squashIt[tid] != instList[tid].end() &&
941 (*squashIt[tid])->seqNum > squashedSeqNum[tid]) {
943 DynInstPtr squashed_inst = (*squashIt[tid]);
945 // Only handle the instruction if it actually is in the IQ and
946 // hasn't already been squashed in the IQ.
947 if (squashed_inst->threadNumber != tid ||
948 squashed_inst->isSquashedInIQ()) {
953 if (!squashed_inst->isIssued() ||
954 (squashed_inst->isMemRef()/* &&
955 !squashed_inst->memOpDone*/)) {
957 // Remove the instruction from the dependency list.
958 if (!squashed_inst->isNonSpeculative()) {
960 for (int src_reg_idx = 0;
961 src_reg_idx < squashed_inst->numSrcRegs();
964 PhysRegIndex src_reg =
965 squashed_inst->renamedSrcRegIdx(src_reg_idx);
967 // Only remove it from the dependency graph if it was
968 // placed there in the first place.
969 // HACK: This assumes that instructions woken up from the
970 // dependency chain aren't informed that a specific src
971 // register has become ready. This may not always be true
973 // Instead of doing a linked list traversal, we can just
974 // remove these squashed instructions either at issue time,
975 // or when the register is overwritten. The only downside
976 // to this is it leaves more room for error.
978 if (!squashed_inst->isReadySrcRegIdx(src_reg_idx) &&
979 src_reg < numPhysRegs) {
980 dependGraph[src_reg].remove(squashed_inst);
984 ++iqSquashedOperandsExamined;
987 // Might want to remove producers as well.
989 nonSpecInsts[squashed_inst->seqNum] = NULL;
991 nonSpecInsts.erase(squashed_inst->seqNum);
993 ++iqSquashedNonSpecRemoved;
996 // Might want to also clear out the head of the dependency graph.
998 // Mark it as squashed within the IQ.
999 squashed_inst->setSquashedInIQ();
1001 // @todo: Remove this hack where several statuses are set so the
1002 // inst will flow through the rest of the pipeline.
1003 squashed_inst->setIssued();
1004 squashed_inst->setCanCommit();
1005 // squashed_inst->removeInIQ();
1007 //Update Thread IQ Count
1008 count[squashed_inst->threadNumber]--;
1012 if (numThreads > 1) {
1013 DPRINTF(IQ, "[tid:%i]: Instruction PC %#x squashed.\n",
1014 tid, squashed_inst->readPC());
1016 DPRINTF(IQ, "Instruction PC %#x squashed.\n",
1017 squashed_inst->readPC());
1022 ++iqSquashedInstsExamined;
1026 template <class Impl>
1028 InstQueue<Impl>::DependencyEntry::insert(DynInstPtr &new_inst)
1030 //Add this new, dependent instruction at the head of the dependency
1033 // First create the entry that will be added to the head of the
1034 // dependency chain.
1035 DependencyEntry *new_entry = new DependencyEntry;
1036 new_entry->next = this->next;
1037 new_entry->inst = new_inst;
1039 // Then actually add it to the chain.
1040 this->next = new_entry;
1042 ++mem_alloc_counter;
1045 template <class Impl>
1047 InstQueue<Impl>::DependencyEntry::remove(DynInstPtr &inst_to_remove)
1049 DependencyEntry *prev = this;
1050 DependencyEntry *curr = this->next;
1052 // Make sure curr isn't NULL. Because this instruction is being
1053 // removed from a dependency list, it must have been placed there at
1054 // an earlier time. The dependency chain should not be empty,
1055 // unless the instruction dependent upon it is already ready.
1060 // Find the instruction to remove within the dependency linked list.
1061 while (curr->inst != inst_to_remove) {
1065 assert(curr != NULL);
1068 // Now remove this instruction from the list.
1069 prev->next = curr->next;
1071 --mem_alloc_counter;
1073 // Could push this off to the destructor of DependencyEntry
1079 template <class Impl>
1081 InstQueue<Impl>::addToDependents(DynInstPtr &new_inst)
1083 // Loop through the instruction's source registers, adding
1084 // them to the dependency list if they are not ready.
1085 int8_t total_src_regs = new_inst->numSrcRegs();
1086 bool return_val = false;
1088 for (int src_reg_idx = 0;
1089 src_reg_idx < total_src_regs;
1092 // Only add it to the dependency graph if it's not ready.
1093 if (!new_inst->isReadySrcRegIdx(src_reg_idx)) {
1094 PhysRegIndex src_reg = new_inst->renamedSrcRegIdx(src_reg_idx);
1096 // Check the IQ's scoreboard to make sure the register
1097 // hasn't become ready while the instruction was in flight
1098 // between stages. Only if it really isn't ready should
1099 // it be added to the dependency graph.
1100 if (src_reg >= numPhysRegs) {
1102 } else if (regScoreboard[src_reg] == false) {
1103 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1104 "is being added to the dependency chain.\n",
1105 new_inst->readPC(), src_reg);
1107 dependGraph[src_reg].insert(new_inst);
1109 // Change the return value to indicate that something
1110 // was added to the dependency graph.
1113 DPRINTF(IQ, "Instruction PC %#x has src reg %i that "
1114 "became ready before it reached the IQ.\n",
1115 new_inst->readPC(), src_reg);
1116 // Mark a register ready within the instruction.
1117 new_inst->markSrcRegReady();
1125 template <class Impl>
1127 InstQueue<Impl>::createDependency(DynInstPtr &new_inst)
1129 //Actually nothing really needs to be marked when an
1130 //instruction becomes the producer of a register's value,
1131 //but for convenience a ptr to the producing instruction will
1132 //be placed in the head node of the dependency links.
1133 int8_t total_dest_regs = new_inst->numDestRegs();
1135 for (int dest_reg_idx = 0;
1136 dest_reg_idx < total_dest_regs;
1139 PhysRegIndex dest_reg = new_inst->renamedDestRegIdx(dest_reg_idx);
1141 // Instructions that use the misc regs will have a reg number
1142 // higher than the normal physical registers. In this case these
1143 // registers are not renamed, and there is no need to track
1144 // dependencies as these instructions must be executed at commit.
1145 if (dest_reg >= numPhysRegs) {
1149 if (dependGraph[dest_reg].next) {
1151 panic("Dependency graph %i not empty!", dest_reg);
1154 dependGraph[dest_reg].inst = new_inst;
1156 // Mark the scoreboard to say it's not yet ready.
1157 regScoreboard[dest_reg] = false;
1161 template <class Impl>
1163 InstQueue<Impl>::addIfReady(DynInstPtr &inst)
1165 //If the instruction now has all of its source registers
1166 // available, then add it to the list of ready instructions.
1167 if (inst->readyToIssue()) {
1169 //Add the instruction to the proper ready list.
1170 if (inst->isMemRef()) {
1172 DPRINTF(IQ, "Checking if memory instruction can issue.\n");
1174 // Message to the mem dependence unit that this instruction has
1175 // its registers ready.
1177 // memDepUnit[inst->threadNumber].regsReady(inst);
1182 // OpClass op_class = inst->opClass();
1184 DPRINTF(IQ, "Instruction is ready to issue, putting it onto "
1185 "the ready list, PC %#x opclass:%i [sn:%lli].\n",
1186 inst->readPC(), inst->opClass(), inst->seqNum);
1188 readyInsts.push(inst);
1192 template <class Impl>
1194 InstQueue<Impl>::countInsts()
1196 //ksewell:This works but definitely could use a cleaner write
1197 //with a more intuitive way of counting. Right now it's
1198 //just brute force ....
1201 int total_insts = 0;
1203 for (int i = 0; i < numThreads; ++i) {
1204 ListIt count_it = instList[i].begin();
1206 while (count_it != instList[i].end()) {
1207 if (!(*count_it)->isSquashed() && !(*count_it)->isSquashedInIQ()) {
1208 if (!(*count_it)->isIssued()) {
1210 } else if ((*count_it)->isMemRef() &&
1211 !(*count_it)->memOpDone) {
1212 // Loads that have not been marked as executed still count
1213 // towards the total instructions.
1224 return numEntries - freeEntries;
1228 template <class Impl>
1230 InstQueue<Impl>::dumpDependGraph()
1232 DependencyEntry *curr;
1234 for (int i = 0; i < numPhysRegs; ++i)
1236 curr = &dependGraph[i];
1239 cprintf("dependGraph[%i]: producer: %#x [sn:%lli] consumer: ",
1240 i, curr->inst->readPC(), curr->inst->seqNum);
1242 cprintf("dependGraph[%i]: No producer. consumer: ", i);
1245 while (curr->next != NULL) {
1248 cprintf("%#x [sn:%lli] ",
1249 curr->inst->readPC(), curr->inst->seqNum);
1256 template <class Impl>
1258 InstQueue<Impl>::dumpLists()
1260 for (int i = 0; i < Num_OpClasses; ++i) {
1261 cprintf("Ready list %i size: %i\n", i, readyInsts.size());
1266 cprintf("Non speculative list size: %i\n", nonSpecInsts.size());
1268 NonSpecMapIt non_spec_it = nonSpecInsts.begin();
1269 NonSpecMapIt non_spec_end_it = nonSpecInsts.end();
1271 cprintf("Non speculative list: ");
1273 while (non_spec_it != non_spec_end_it) {
1274 cprintf("%#x [sn:%lli]", (*non_spec_it).second->readPC(),
1275 (*non_spec_it).second->seqNum);
1281 ListOrderIt list_order_it = listOrder.begin();
1282 ListOrderIt list_order_end_it = listOrder.end();
1285 cprintf("List order: ");
1287 while (list_order_it != list_order_end_it) {
1288 cprintf("%i OpClass:%i [sn:%lli] ", i, (*list_order_it).queueType,
1289 (*list_order_it).oldestInst);
1299 template <class Impl>
1301 InstQueue<Impl>::dumpInsts()
1303 for (int i = 0; i < numThreads; ++i) {
1305 // int valid_num = 0;
1307 ListIt inst_list_it = instList[i].begin();
1309 while (inst_list_it != instList[i].end())
1311 cprintf("Instruction:%i\n",
1313 if (!(*inst_list_it)->isSquashed()) {
1314 if (!(*inst_list_it)->isIssued()) {
1316 cprintf("Count:%i\n", valid_num);
1317 } else if ((*inst_list_it)->isMemRef() &&
1318 !(*inst_list_it)->memOpDone) {
1319 // Loads that have not been marked as executed still count
1320 // towards the total instructions.
1322 cprintf("Count:%i\n", valid_num);
1326 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1327 "Issued:%i\nSquashed:%i\n",
1328 (*inst_list_it)->readPC(),
1329 (*inst_list_it)->seqNum,
1330 (*inst_list_it)->threadNumber,
1331 (*inst_list_it)->isIssued(),
1332 (*inst_list_it)->isSquashed());
1334 if ((*inst_list_it)->isMemRef()) {
1335 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);