2 * Copyright (c) 2006 The Regents of The University of Michigan
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31 #ifndef __CPU_OZONE_LW_BACK_END_HH__
32 #define __CPU_OZONE_LW_BACK_END_HH__
39 #include "arch/faults.hh"
40 #include "base/timebuf.hh"
41 #include "cpu/inst_seq.hh"
42 #include "cpu/ozone/rename_table.hh"
43 #include "cpu/ozone/thread_state.hh"
44 #include "mem/request.hh"
45 #include "sim/eventq.hh"
52 class OzoneThreadState;
58 typedef OzoneThreadState<Impl> Thread;
60 typedef typename Impl::Params Params;
61 typedef typename Impl::DynInst DynInst;
62 typedef typename Impl::DynInstPtr DynInstPtr;
63 typedef typename Impl::FullCPU FullCPU;
64 typedef typename Impl::FrontEnd FrontEnd;
65 typedef typename Impl::FullCPU::CommStruct CommStruct;
71 typedef SizeStruct DispatchToIssue;
72 typedef SizeStruct IssueToExec;
73 typedef SizeStruct ExecToCommit;
74 typedef SizeStruct Writeback;
76 TimeBuffer<DispatchToIssue> d2i;
77 typename TimeBuffer<DispatchToIssue>::wire instsToDispatch;
78 TimeBuffer<IssueToExec> i2e;
79 typename TimeBuffer<IssueToExec>::wire instsToExecute;
80 TimeBuffer<ExecToCommit> e2c;
81 TimeBuffer<Writeback> numInstsToWB;
83 TimeBuffer<CommStruct> *comm;
84 typename TimeBuffer<CommStruct>::wire toIEW;
85 typename TimeBuffer<CommStruct>::wire fromCommit;
87 class TrapEvent : public Event {
92 TrapEvent(LWBackEnd<Impl> *_be);
95 const char *description();
98 /** LdWriteback event for a load completion. */
99 class LdWritebackEvent : public Event {
101 /** Instruction that is writing back data to the register file. */
103 /** Pointer to IEW stage. */
109 /** Constructs a load writeback event. */
110 LdWritebackEvent(DynInstPtr &_inst, LWBackEnd *be);
112 /** Processes writeback event. */
113 virtual void process();
114 /** Returns the description of the writeback event. */
115 virtual const char *description();
117 void setDcacheMiss() { dcacheMiss = true; be->addDcacheMiss(inst); }
120 LWBackEnd(Params *params);
122 std::string name() const;
126 void setCPU(FullCPU *cpu_ptr);
128 void setFrontEnd(FrontEnd *front_end_ptr)
129 { frontEnd = front_end_ptr; }
131 void setTC(ThreadContext *tc_ptr)
134 void setThreadState(Thread *thread_ptr)
135 { thread = thread_ptr; }
137 void setCommBuffer(TimeBuffer<CommStruct> *_comm);
141 void generateTCEvent() { tcSquash = true; }
143 void squashFromTrap();
144 void checkInterrupts();
149 Fault read(RequestPtr req, T &data, int load_idx);
152 Fault write(RequestPtr req, T &data, int store_idx);
154 Addr readCommitPC() { return commitPC; }
158 Tick lastCommitCycle;
160 bool robEmpty() { return instList.empty(); }
162 bool isFull() { return numInsts >= numROBEntries; }
163 bool isBlocked() { return status == Blocked || dispatchStatus == Blocked; }
165 void fetchFault(Fault &fault);
167 int wakeDependents(DynInstPtr &inst, bool memory_deps = false);
169 /** Tells memory dependence unit that a memory instruction needs to be
170 * rescheduled. It will re-execute once replayMemInst() is called.
172 void rescheduleMemInst(DynInstPtr &inst);
174 /** Re-executes all rescheduled memory instructions. */
175 void replayMemInst(DynInstPtr &inst);
177 /** Completes memory instruction. */
178 void completeMemInst(DynInstPtr &inst) { }
180 void addDcacheMiss(DynInstPtr &inst)
182 waitingMemOps.insert(inst->seqNum);
184 DPRINTF(BE, "Adding a Dcache miss mem op [sn:%lli], total %i\n",
185 inst->seqNum, numWaitingMemOps);
188 void removeDcacheMiss(DynInstPtr &inst)
190 assert(waitingMemOps.find(inst->seqNum) != waitingMemOps.end());
191 waitingMemOps.erase(inst->seqNum);
193 DPRINTF(BE, "Removing a Dcache miss mem op [sn:%lli], total %i\n",
194 inst->seqNum, numWaitingMemOps);
197 void addWaitingMemOp(DynInstPtr &inst)
199 waitingMemOps.insert(inst->seqNum);
201 DPRINTF(BE, "Adding a waiting mem op [sn:%lli], total %i\n",
202 inst->seqNum, numWaitingMemOps);
205 void removeWaitingMemOp(DynInstPtr &inst)
207 assert(waitingMemOps.find(inst->seqNum) != waitingMemOps.end());
208 waitingMemOps.erase(inst->seqNum);
210 DPRINTF(BE, "Removing a waiting mem op [sn:%lli], total %i\n",
211 inst->seqNum, numWaitingMemOps);
214 void instToCommit(DynInstPtr &inst);
218 void takeOverFrom(ThreadContext *old_tc = NULL);
220 bool isSwitchedOut() { return switchedOut; }
223 void generateTrapEvent(Tick latency = 0);
224 void handleFault(Fault &fault, Tick latency = 0);
225 void updateStructures();
226 void dispatchInsts();
227 void dispatchStall();
228 void checkDispatchStatus();
231 void addToLSQ(DynInstPtr &inst);
232 void writebackInsts();
233 bool commitInst(int inst_num);
234 void squash(const InstSeqNum &sn);
235 void squashDueToBranch(DynInstPtr &inst);
236 void squashDueToMemViolation(DynInstPtr &inst);
237 void squashDueToMemBlocked(DynInstPtr &inst);
238 void updateExeInstStats(DynInstPtr &inst);
239 void updateComInstStats(DynInstPtr &inst);
261 Status dispatchStatus;
268 typedef typename Impl::LdstQueue LdstQueue;
272 RenameTable<Impl> commitRenameTable;
274 RenameTable<Impl> renameTable;
276 class DCacheCompletionEvent : public Event
282 DCacheCompletionEvent(LWBackEnd *_be);
284 virtual void process();
285 virtual const char *description();
288 friend class DCacheCompletionEvent;
290 DCacheCompletionEvent cacheCompletionEvent;
292 MemInterface *dcacheInterface;
294 // General back end width. Used if the more specific isn't given.
299 int numDispatchEntries;
312 /** Index into queue of instructions being written back. */
315 /** Cycle number within the queue of instructions being written
316 * back. Used in case there are too many instructions writing
317 * back at the current cycle and writesbacks need to be scheduled
318 * for the future. See comments in instToCommit().
325 std::set<InstSeqNum> waitingMemOps;
326 typedef std::set<InstSeqNum>::iterator MemIt;
327 int numWaitingMemOps;
328 unsigned maxOutstandingMemOps;
331 InstSeqNum squashSeqNum;
334 Fault faultFromFetch;
340 DynInstPtr memBarrier;
344 bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
346 return lhs->seqNum > rhs->seqNum;
350 typedef typename std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> ReadyInstQueue;
351 ReadyInstQueue exeList;
353 typedef typename std::list<DynInstPtr>::iterator InstListIt;
355 std::list<DynInstPtr> instList;
356 std::list<DynInstPtr> waitingList;
357 std::list<DynInstPtr> replayList;
358 std::list<DynInstPtr> writeback;
366 // number of cycles stalled for D-cache misses
367 /* Stats::Scalar<> dcacheStallCycles;
368 Counter lastDcacheStall;
370 Stats::Vector<> rob_cap_events;
371 Stats::Vector<> rob_cap_inst_count;
372 Stats::Vector<> iq_cap_events;
373 Stats::Vector<> iq_cap_inst_count;
374 // total number of instructions executed
375 Stats::Vector<> exe_inst;
376 Stats::Vector<> exe_swp;
377 Stats::Vector<> exe_nop;
378 Stats::Vector<> exe_refs;
379 Stats::Vector<> exe_loads;
380 Stats::Vector<> exe_branches;
382 Stats::Vector<> issued_ops;
384 // total number of loads forwaded from LSQ stores
385 Stats::Vector<> lsq_forw_loads;
387 // total number of loads ignored due to invalid addresses
388 Stats::Vector<> inv_addr_loads;
390 // total number of software prefetches ignored due to invalid addresses
391 Stats::Vector<> inv_addr_swpfs;
392 // ready loads blocked due to memory disambiguation
393 Stats::Vector<> lsq_blocked_loads;
395 Stats::Scalar<> lsqInversion;
397 Stats::Vector<> n_issued_dist;
398 Stats::VectorDistribution<> issue_delay_dist;
400 Stats::VectorDistribution<> queue_res_dist;
402 Stats::Vector<> stat_fu_busy;
403 Stats::Vector2d<> stat_fuBusy;
404 Stats::Vector<> dist_unissued;
405 Stats::Vector2d<> stat_issued_inst_type;
407 Stats::Formula misspec_cnt;
408 Stats::Formula misspec_ipc;
409 Stats::Formula issue_rate;
410 Stats::Formula issue_stores;
411 Stats::Formula issue_op_rate;
412 Stats::Formula fu_busy_rate;
413 Stats::Formula commit_stores;
414 Stats::Formula commit_ipc;
415 Stats::Formula commit_ipb;
416 Stats::Formula lsq_inv_rate;
418 Stats::Vector<> writeback_count;
419 Stats::Vector<> producer_inst;
420 Stats::Vector<> consumer_inst;
421 Stats::Vector<> wb_penalized;
423 Stats::Formula wb_rate;
424 Stats::Formula wb_fanout;
425 Stats::Formula wb_penalized_rate;
427 // total number of instructions committed
428 Stats::Vector<> stat_com_inst;
429 Stats::Vector<> stat_com_swp;
430 Stats::Vector<> stat_com_refs;
431 Stats::Vector<> stat_com_loads;
432 Stats::Vector<> stat_com_membars;
433 Stats::Vector<> stat_com_branches;
435 Stats::Distribution<> n_committed_dist;
437 Stats::Scalar<> commit_eligible_samples;
438 Stats::Vector<> commit_eligible;
440 Stats::Vector<> squashedInsts;
441 Stats::Vector<> ROBSquashedInsts;
443 Stats::Scalar<> ROB_fcount;
444 Stats::Formula ROB_full_rate;
446 Stats::Vector<> ROB_count; // cumulative ROB occupancy
447 Stats::Formula ROB_occ_rate;
448 Stats::VectorDistribution<> ROB_occ_dist;
452 Checker<DynInstPtr> *checker;
455 template <class Impl>
458 LWBackEnd<Impl>::read(RequestPtr req, T &data, int load_idx)
460 return LSQ.read(req, data, load_idx);
463 template <class Impl>
466 LWBackEnd<Impl>::write(RequestPtr req, T &data, int store_idx)
468 return LSQ.write(req, data, store_idx);
471 #endif // __CPU_OZONE_LW_BACK_END_HH__