src/cpu/ozone/lw_back_end.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_OZONE_LW_BACK_END_HH__
  32 #define __CPU_OZONE_LW_BACK_END_HH__
  33
  34 #include <list>
  35 #include <queue>
  36 #include <set>
  37 #include <string>
  38
  39 #include "arch/faults.hh"
  40 #include "base/timebuf.hh"
  41 #include "cpu/inst_seq.hh"
  42 #include "cpu/ozone/rename_table.hh"
  43 #include "cpu/ozone/thread_state.hh"
  44 #include "mem/request.hh"
  45 #include "sim/eventq.hh"
  46
  47 template <class>
  48 class Checker;
  49 class ThreadContext;
  50
  51 template <class Impl>
  52 class OzoneThreadState;
  53
  54 template <class Impl>
  55 class LWBackEnd
  56 {
  57   public:
  58     typedef OzoneThreadState<Impl> Thread;
  59
  60     typedef typename Impl::Params Params;
  61     typedef typename Impl::DynInst DynInst;
  62     typedef typename Impl::DynInstPtr DynInstPtr;
  63     typedef typename Impl::FullCPU FullCPU;
  64     typedef typename Impl::FrontEnd FrontEnd;
  65     typedef typename Impl::FullCPU::CommStruct CommStruct;
  66
  67     struct SizeStruct {
  68         int size;
  69     };
  70
  71     typedef SizeStruct DispatchToIssue;
  72     typedef SizeStruct IssueToExec;
  73     typedef SizeStruct ExecToCommit;
  74     typedef SizeStruct Writeback;
  75
  76     TimeBuffer<DispatchToIssue> d2i;
  77     typename TimeBuffer<DispatchToIssue>::wire instsToDispatch;
  78     TimeBuffer<IssueToExec> i2e;
  79     typename TimeBuffer<IssueToExec>::wire instsToExecute;
  80     TimeBuffer<ExecToCommit> e2c;
  81     TimeBuffer<Writeback> numInstsToWB;
  82
  83     TimeBuffer<CommStruct> *comm;
  84     typename TimeBuffer<CommStruct>::wire toIEW;
  85     typename TimeBuffer<CommStruct>::wire fromCommit;
  86
  87     class TrapEvent : public Event {
  88       private:
  89         LWBackEnd<Impl> *be;
  90
  91       public:
  92         TrapEvent(LWBackEnd<Impl> *_be);
  93
  94         void process();
  95         const char *description();
  96     };
  97
  98     /** LdWriteback event for a load completion. */
  99     class LdWritebackEvent : public Event {
 100       private:
 101         /** Instruction that is writing back data to the register file. */
 102         DynInstPtr inst;
 103         /** Pointer to IEW stage. */
 104         LWBackEnd *be;
 105
 106         bool dcacheMiss;
 107
 108       public:
 109         /** Constructs a load writeback event. */
 110         LdWritebackEvent(DynInstPtr &_inst, LWBackEnd *be);
 111
 112         /** Processes writeback event. */
 113         virtual void process();
 114         /** Returns the description of the writeback event. */
 115         virtual const char *description();
 116
 117         void setDcacheMiss() { dcacheMiss = true; be->addDcacheMiss(inst); }
 118     };
 119
 120     LWBackEnd(Params *params);
 121
 122     std::string name() const;
 123
 124     void regStats();
 125
 126     void setCPU(FullCPU *cpu_ptr);
 127
 128     void setFrontEnd(FrontEnd *front_end_ptr)
 129     { frontEnd = front_end_ptr; }
 130
 131     void setTC(ThreadContext *tc_ptr)
 132     { tc = tc_ptr; }
 133
 134     void setThreadState(Thread *thread_ptr)
 135     { thread = thread_ptr; }
 136
 137     void setCommBuffer(TimeBuffer<CommStruct> *_comm);
 138
 139     void tick();
 140     void squash();
 141     void generateTCEvent() { tcSquash = true; }
 142     void squashFromTC();
 143     void squashFromTrap();
 144     void checkInterrupts();
 145     bool trapSquash;
 146     bool tcSquash;
 147
 148     template <class T>
 149     Fault read(RequestPtr req, T &data, int load_idx);
 150
 151     template <class T>
 152     Fault write(RequestPtr req, T &data, int store_idx);
 153
 154     Addr readCommitPC() { return commitPC; }
 155
 156     Addr commitPC;
 157
 158     Tick lastCommitCycle;
 159
 160     bool robEmpty() { return instList.empty(); }
 161
 162     bool isFull() { return numInsts >= numROBEntries; }
 163     bool isBlocked() { return status == Blocked || dispatchStatus == Blocked; }
 164
 165     void fetchFault(Fault &fault);
 166
 167     int wakeDependents(DynInstPtr &inst, bool memory_deps = false);
 168
 169     /** Tells memory dependence unit that a memory instruction needs to be
 170      * rescheduled. It will re-execute once replayMemInst() is called.
 171      */
 172     void rescheduleMemInst(DynInstPtr &inst);
 173
 174     /** Re-executes all rescheduled memory instructions. */
 175     void replayMemInst(DynInstPtr &inst);
 176
 177     /** Completes memory instruction. */
 178     void completeMemInst(DynInstPtr &inst) { }
 179
 180     void addDcacheMiss(DynInstPtr &inst)
 181     {
 182         waitingMemOps.insert(inst->seqNum);
 183         numWaitingMemOps++;
 184         DPRINTF(BE, "Adding a Dcache miss mem op [sn:%lli], total %i\n",
 185                 inst->seqNum, numWaitingMemOps);
 186     }
 187
 188     void removeDcacheMiss(DynInstPtr &inst)
 189     {
 190         assert(waitingMemOps.find(inst->seqNum) != waitingMemOps.end());
 191         waitingMemOps.erase(inst->seqNum);
 192         numWaitingMemOps--;
 193         DPRINTF(BE, "Removing a Dcache miss mem op [sn:%lli], total %i\n",
 194                 inst->seqNum, numWaitingMemOps);
 195     }
 196
 197     void addWaitingMemOp(DynInstPtr &inst)
 198     {
 199         waitingMemOps.insert(inst->seqNum);
 200         numWaitingMemOps++;
 201         DPRINTF(BE, "Adding a waiting mem op [sn:%lli], total %i\n",
 202                 inst->seqNum, numWaitingMemOps);
 203     }
 204
 205     void removeWaitingMemOp(DynInstPtr &inst)
 206     {
 207         assert(waitingMemOps.find(inst->seqNum) != waitingMemOps.end());
 208         waitingMemOps.erase(inst->seqNum);
 209         numWaitingMemOps--;
 210         DPRINTF(BE, "Removing a waiting mem op [sn:%lli], total %i\n",
 211                 inst->seqNum, numWaitingMemOps);
 212     }
 213
 214     void instToCommit(DynInstPtr &inst);
 215
 216     void switchOut();
 217     void doSwitchOut();
 218     void takeOverFrom(ThreadContext *old_tc = NULL);
 219
 220     bool isSwitchedOut() { return switchedOut; }
 221
 222   private:
 223     void generateTrapEvent(Tick latency = 0);
 224     void handleFault(Fault &fault, Tick latency = 0);
 225     void updateStructures();
 226     void dispatchInsts();
 227     void dispatchStall();
 228     void checkDispatchStatus();
 229     void executeInsts();
 230     void commitInsts();
 231     void addToLSQ(DynInstPtr &inst);
 232     void writebackInsts();
 233     bool commitInst(int inst_num);
 234     void squash(const InstSeqNum &sn);
 235     void squashDueToBranch(DynInstPtr &inst);
 236     void squashDueToMemViolation(DynInstPtr &inst);
 237     void squashDueToMemBlocked(DynInstPtr &inst);
 238     void updateExeInstStats(DynInstPtr &inst);
 239     void updateComInstStats(DynInstPtr &inst);
 240
 241   public:
 242     FullCPU *cpu;
 243
 244     FrontEnd *frontEnd;
 245
 246     ThreadContext *tc;
 247
 248     Thread *thread;
 249
 250     enum Status {
 251         Running,
 252         Idle,
 253         DcacheMissStall,
 254         DcacheMissComplete,
 255         Blocked,
 256         TrapPending
 257     };
 258
 259     Status status;
 260
 261     Status dispatchStatus;
 262
 263     Status commitStatus;
 264
 265     Counter funcExeInst;
 266
 267   private:
 268     typedef typename Impl::LdstQueue LdstQueue;
 269
 270     LdstQueue LSQ;
 271   public:
 272     RenameTable<Impl> commitRenameTable;
 273
 274     RenameTable<Impl> renameTable;
 275   private:
 276     class DCacheCompletionEvent : public Event
 277     {
 278       private:
 279         LWBackEnd *be;
 280
 281       public:
 282         DCacheCompletionEvent(LWBackEnd *_be);
 283
 284         virtual void process();
 285         virtual const char *description();
 286     };
 287
 288     friend class DCacheCompletionEvent;
 289
 290     DCacheCompletionEvent cacheCompletionEvent;
 291
 292     MemInterface *dcacheInterface;
 293
 294     // General back end width. Used if the more specific isn't given.
 295     int width;
 296
 297     // Dispatch width.
 298     int dispatchWidth;
 299     int numDispatchEntries;
 300     int dispatchSize;
 301
 302     int waitingInsts;
 303
 304     int issueWidth;
 305
 306     // Writeback width
 307     int wbWidth;
 308
 309     // Commit width
 310     int commitWidth;
 311
 312     /** Index into queue of instructions being written back. */
 313     unsigned wbNumInst;
 314
 315     /** Cycle number within the queue of instructions being written
 316      * back.  Used in case there are too many instructions writing
 317      * back at the current cycle and writesbacks need to be scheduled
 318      * for the future. See comments in instToCommit().
 319      */
 320     unsigned wbCycle;
 321
 322     int numROBEntries;
 323     int numInsts;
 324
 325     std::set<InstSeqNum> waitingMemOps;
 326     typedef std::set<InstSeqNum>::iterator MemIt;
 327     int numWaitingMemOps;
 328     unsigned maxOutstandingMemOps;
 329
 330     bool squashPending;
 331     InstSeqNum squashSeqNum;
 332     Addr squashNextPC;
 333
 334     Fault faultFromFetch;
 335     bool fetchHasFault;
 336
 337     bool switchedOut;
 338     bool switchPending;
 339
 340     DynInstPtr memBarrier;
 341
 342   private:
 343     struct pqCompare {
 344         bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
 345         {
 346             return lhs->seqNum > rhs->seqNum;
 347         }
 348     };
 349
 350     typedef typename std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> ReadyInstQueue;
 351     ReadyInstQueue exeList;
 352
 353     typedef typename std::list<DynInstPtr>::iterator InstListIt;
 354
 355     std::list<DynInstPtr> instList;
 356     std::list<DynInstPtr> waitingList;
 357     std::list<DynInstPtr> replayList;
 358     std::list<DynInstPtr> writeback;
 359
 360     int latency;
 361
 362     int squashLatency;
 363
 364     bool exactFullStall;
 365
 366     // number of cycles stalled for D-cache misses
 367 /*    Stats::Scalar<> dcacheStallCycles;
 368       Counter lastDcacheStall;
 369 */
 370     Stats::Vector<> rob_cap_events;
 371     Stats::Vector<> rob_cap_inst_count;
 372     Stats::Vector<> iq_cap_events;
 373     Stats::Vector<> iq_cap_inst_count;
 374     // total number of instructions executed
 375     Stats::Vector<> exe_inst;
 376     Stats::Vector<> exe_swp;
 377     Stats::Vector<> exe_nop;
 378     Stats::Vector<> exe_refs;
 379     Stats::Vector<> exe_loads;
 380     Stats::Vector<> exe_branches;
 381
 382     Stats::Vector<> issued_ops;
 383
 384     // total number of loads forwaded from LSQ stores
 385     Stats::Vector<> lsq_forw_loads;
 386
 387     // total number of loads ignored due to invalid addresses
 388     Stats::Vector<> inv_addr_loads;
 389
 390     // total number of software prefetches ignored due to invalid addresses
 391     Stats::Vector<> inv_addr_swpfs;
 392     // ready loads blocked due to memory disambiguation
 393     Stats::Vector<> lsq_blocked_loads;
 394
 395     Stats::Scalar<> lsqInversion;
 396
 397     Stats::Vector<> n_issued_dist;
 398     Stats::VectorDistribution<> issue_delay_dist;
 399
 400     Stats::VectorDistribution<> queue_res_dist;
 401 /*
 402     Stats::Vector<> stat_fu_busy;
 403     Stats::Vector2d<> stat_fuBusy;
 404     Stats::Vector<> dist_unissued;
 405     Stats::Vector2d<> stat_issued_inst_type;
 406
 407     Stats::Formula misspec_cnt;
 408     Stats::Formula misspec_ipc;
 409     Stats::Formula issue_rate;
 410     Stats::Formula issue_stores;
 411     Stats::Formula issue_op_rate;
 412     Stats::Formula fu_busy_rate;
 413     Stats::Formula commit_stores;
 414     Stats::Formula commit_ipc;
 415     Stats::Formula commit_ipb;
 416     Stats::Formula lsq_inv_rate;
 417 */
 418     Stats::Vector<> writeback_count;
 419     Stats::Vector<> producer_inst;
 420     Stats::Vector<> consumer_inst;
 421     Stats::Vector<> wb_penalized;
 422
 423     Stats::Formula wb_rate;
 424     Stats::Formula wb_fanout;
 425     Stats::Formula wb_penalized_rate;
 426
 427     // total number of instructions committed
 428     Stats::Vector<> stat_com_inst;
 429     Stats::Vector<> stat_com_swp;
 430     Stats::Vector<> stat_com_refs;
 431     Stats::Vector<> stat_com_loads;
 432     Stats::Vector<> stat_com_membars;
 433     Stats::Vector<> stat_com_branches;
 434
 435     Stats::Distribution<> n_committed_dist;
 436
 437     Stats::Scalar<> commit_eligible_samples;
 438     Stats::Vector<> commit_eligible;
 439
 440     Stats::Vector<> squashedInsts;
 441     Stats::Vector<> ROBSquashedInsts;
 442
 443     Stats::Scalar<> ROB_fcount;
 444     Stats::Formula ROB_full_rate;
 445
 446     Stats::Vector<>  ROB_count;  // cumulative ROB occupancy
 447     Stats::Formula ROB_occ_rate;
 448     Stats::VectorDistribution<> ROB_occ_dist;
 449   public:
 450     void dumpInsts();
 451
 452     Checker<DynInstPtr> *checker;
 453 };
 454
 455 template <class Impl>
 456 template <class T>
 457 Fault
 458 LWBackEnd<Impl>::read(RequestPtr req, T &data, int load_idx)
 459 {
 460     return LSQ.read(req, data, load_idx);
 461 }
 462
 463 template <class Impl>
 464 template <class T>
 465 Fault
 466 LWBackEnd<Impl>::write(RequestPtr req, T &data, int store_idx)
 467 {
 468     return LSQ.write(req, data, store_idx);
 469 }
 470
 471 #endif // __CPU_OZONE_LW_BACK_END_HH__