2 * Copyright (c) 2006 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
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31 #ifndef __CPU_OZONE_LW_BACK_END_HH__
32 #define __CPU_OZONE_LW_BACK_END_HH__
39 #include "arch/faults.hh"
40 #include "base/timebuf.hh"
41 #include "cpu/inst_seq.hh"
42 #include "cpu/ozone/rename_table.hh"
43 #include "cpu/ozone/thread_state.hh"
44 #include "mem/request.hh"
45 #include "sim/eventq.hh"
52 class OzoneThreadState;
60 typedef OzoneThreadState<Impl> Thread;
62 typedef typename Impl::Params Params;
63 typedef typename Impl::DynInst DynInst;
64 typedef typename Impl::DynInstPtr DynInstPtr;
65 typedef typename Impl::OzoneCPU OzoneCPU;
66 typedef typename Impl::FrontEnd FrontEnd;
67 typedef typename Impl::OzoneCPU::CommStruct CommStruct;
73 typedef SizeStruct DispatchToIssue;
74 typedef SizeStruct IssueToExec;
75 typedef SizeStruct ExecToCommit;
76 typedef SizeStruct Writeback;
78 TimeBuffer<DispatchToIssue> d2i;
79 typename TimeBuffer<DispatchToIssue>::wire instsToDispatch;
80 TimeBuffer<IssueToExec> i2e;
81 typename TimeBuffer<IssueToExec>::wire instsToExecute;
82 TimeBuffer<ExecToCommit> e2c;
83 TimeBuffer<Writeback> numInstsToWB;
85 TimeBuffer<CommStruct> *comm;
86 typename TimeBuffer<CommStruct>::wire toIEW;
87 typename TimeBuffer<CommStruct>::wire fromCommit;
89 class TrapEvent : public Event {
94 TrapEvent(LWBackEnd<Impl> *_be);
97 const char *description();
100 LWBackEnd(Params *params);
102 std::string name() const;
106 void setCPU(OzoneCPU *cpu_ptr);
108 void setFrontEnd(FrontEnd *front_end_ptr)
109 { frontEnd = front_end_ptr; }
111 void setTC(ThreadContext *tc_ptr)
114 void setThreadState(Thread *thread_ptr)
115 { thread = thread_ptr; }
117 void setCommBuffer(TimeBuffer<CommStruct> *_comm);
119 Port *getDcachePort() { return LSQ.getDcachePort(); }
123 void generateTCEvent() { tcSquash = true; }
125 void squashFromTrap();
126 void checkInterrupts();
131 Fault read(RequestPtr req, T &data, int load_idx);
134 Fault write(RequestPtr req, T &data, int store_idx);
136 Addr readCommitPC() { return commitPC; }
140 Tick lastCommitCycle;
142 bool robEmpty() { return instList.empty(); }
144 bool isFull() { return numInsts >= numROBEntries; }
145 bool isBlocked() { return status == Blocked || dispatchStatus == Blocked; }
147 void fetchFault(Fault &fault);
149 int wakeDependents(DynInstPtr &inst, bool memory_deps = false);
151 /** Tells memory dependence unit that a memory instruction needs to be
152 * rescheduled. It will re-execute once replayMemInst() is called.
154 void rescheduleMemInst(DynInstPtr &inst);
156 /** Re-executes all rescheduled memory instructions. */
157 void replayMemInst(DynInstPtr &inst);
159 /** Completes memory instruction. */
160 void completeMemInst(DynInstPtr &inst) { }
162 void addDcacheMiss(DynInstPtr &inst)
164 waitingMemOps.insert(inst->seqNum);
166 DPRINTF(BE, "Adding a Dcache miss mem op [sn:%lli], total %i\n",
167 inst->seqNum, numWaitingMemOps);
170 void removeDcacheMiss(DynInstPtr &inst)
172 assert(waitingMemOps.find(inst->seqNum) != waitingMemOps.end());
173 waitingMemOps.erase(inst->seqNum);
175 DPRINTF(BE, "Removing a Dcache miss mem op [sn:%lli], total %i\n",
176 inst->seqNum, numWaitingMemOps);
179 void addWaitingMemOp(DynInstPtr &inst)
181 waitingMemOps.insert(inst->seqNum);
183 DPRINTF(BE, "Adding a waiting mem op [sn:%lli], total %i\n",
184 inst->seqNum, numWaitingMemOps);
187 void removeWaitingMemOp(DynInstPtr &inst)
189 assert(waitingMemOps.find(inst->seqNum) != waitingMemOps.end());
190 waitingMemOps.erase(inst->seqNum);
192 DPRINTF(BE, "Removing a waiting mem op [sn:%lli], total %i\n",
193 inst->seqNum, numWaitingMemOps);
196 void instToCommit(DynInstPtr &inst);
200 void takeOverFrom(ThreadContext *old_tc = NULL);
202 bool isSwitchedOut() { return switchedOut; }
205 void generateTrapEvent(Tick latency = 0);
206 void handleFault(Fault &fault, Tick latency = 0);
207 void updateStructures();
208 void dispatchInsts();
209 void dispatchStall();
210 void checkDispatchStatus();
213 void addToLSQ(DynInstPtr &inst);
214 void writebackInsts();
215 bool commitInst(int inst_num);
216 void squash(const InstSeqNum &sn);
217 void squashDueToBranch(DynInstPtr &inst);
218 void squashDueToMemViolation(DynInstPtr &inst);
219 void squashDueToMemBlocked(DynInstPtr &inst);
220 void updateExeInstStats(DynInstPtr &inst);
221 void updateComInstStats(DynInstPtr &inst);
243 Status dispatchStatus;
250 typedef typename Impl::LdstQueue LdstQueue;
254 RenameTable<Impl> commitRenameTable;
256 RenameTable<Impl> renameTable;
258 // General back end width. Used if the more specific isn't given.
263 int numDispatchEntries;
276 /** Index into queue of instructions being written back. */
279 /** Cycle number within the queue of instructions being written
280 * back. Used in case there are too many instructions writing
281 * back at the current cycle and writesbacks need to be scheduled
282 * for the future. See comments in instToCommit().
289 std::set<InstSeqNum> waitingMemOps;
290 typedef std::set<InstSeqNum>::iterator MemIt;
291 int numWaitingMemOps;
292 unsigned maxOutstandingMemOps;
295 InstSeqNum squashSeqNum;
298 Fault faultFromFetch;
304 DynInstPtr memBarrier;
308 bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
310 return lhs->seqNum > rhs->seqNum;
314 typedef typename std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> ReadyInstQueue;
315 ReadyInstQueue exeList;
317 typedef typename std::list<DynInstPtr>::iterator InstListIt;
319 std::list<DynInstPtr> instList;
320 std::list<DynInstPtr> waitingList;
321 std::list<DynInstPtr> replayList;
322 std::list<DynInstPtr> writeback;
330 // number of cycles stalled for D-cache misses
331 /* Stats::Scalar<> dcacheStallCycles;
332 Counter lastDcacheStall;
334 Stats::Vector<> rob_cap_events;
335 Stats::Vector<> rob_cap_inst_count;
336 Stats::Vector<> iq_cap_events;
337 Stats::Vector<> iq_cap_inst_count;
338 // total number of instructions executed
339 Stats::Vector<> exe_inst;
340 Stats::Vector<> exe_swp;
341 Stats::Vector<> exe_nop;
342 Stats::Vector<> exe_refs;
343 Stats::Vector<> exe_loads;
344 Stats::Vector<> exe_branches;
346 Stats::Vector<> issued_ops;
348 // total number of loads forwaded from LSQ stores
349 Stats::Vector<> lsq_forw_loads;
351 // total number of loads ignored due to invalid addresses
352 Stats::Vector<> inv_addr_loads;
354 // total number of software prefetches ignored due to invalid addresses
355 Stats::Vector<> inv_addr_swpfs;
356 // ready loads blocked due to memory disambiguation
357 Stats::Vector<> lsq_blocked_loads;
359 Stats::Scalar<> lsqInversion;
361 Stats::Vector<> n_issued_dist;
362 Stats::VectorDistribution<> issue_delay_dist;
364 Stats::VectorDistribution<> queue_res_dist;
366 Stats::Vector<> stat_fu_busy;
367 Stats::Vector2d<> stat_fuBusy;
368 Stats::Vector<> dist_unissued;
369 Stats::Vector2d<> stat_issued_inst_type;
371 Stats::Formula misspec_cnt;
372 Stats::Formula misspec_ipc;
373 Stats::Formula issue_rate;
374 Stats::Formula issue_stores;
375 Stats::Formula issue_op_rate;
376 Stats::Formula fu_busy_rate;
377 Stats::Formula commit_stores;
378 Stats::Formula commit_ipc;
379 Stats::Formula commit_ipb;
380 Stats::Formula lsq_inv_rate;
382 Stats::Vector<> writeback_count;
383 Stats::Vector<> producer_inst;
384 Stats::Vector<> consumer_inst;
385 Stats::Vector<> wb_penalized;
387 Stats::Formula wb_rate;
388 Stats::Formula wb_fanout;
389 Stats::Formula wb_penalized_rate;
391 // total number of instructions committed
392 Stats::Vector<> stat_com_inst;
393 Stats::Vector<> stat_com_swp;
394 Stats::Vector<> stat_com_refs;
395 Stats::Vector<> stat_com_loads;
396 Stats::Vector<> stat_com_membars;
397 Stats::Vector<> stat_com_branches;
399 Stats::Distribution<> n_committed_dist;
401 Stats::Scalar<> commit_eligible_samples;
402 Stats::Vector<> commit_eligible;
404 Stats::Vector<> squashedInsts;
405 Stats::Vector<> ROBSquashedInsts;
407 Stats::Scalar<> ROB_fcount;
408 Stats::Formula ROB_full_rate;
410 Stats::Vector<> ROB_count; // cumulative ROB occupancy
411 Stats::Formula ROB_occ_rate;
412 Stats::VectorDistribution<> ROB_occ_dist;
416 Checker<DynInstPtr> *checker;
419 template <class Impl>
422 LWBackEnd<Impl>::read(RequestPtr req, T &data, int load_idx)
424 return LSQ.read(req, data, load_idx);
427 template <class Impl>
430 LWBackEnd<Impl>::write(RequestPtr req, T &data, int store_idx)
432 return LSQ.write(req, data, store_idx);
435 #endif // __CPU_OZONE_LW_BACK_END_HH__