src/cpu/ozone/lw_back_end.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_OZONE_LW_BACK_END_HH__
  30 #define __CPU_OZONE_LW_BACK_END_HH__
  31
  32 #include <list>
  33 #include <queue>
  34 #include <set>
  35 #include <string>
  36
  37 #include "arch/faults.hh"
  38 #include "base/timebuf.hh"
  39 #include "cpu/inst_seq.hh"
  40 #include "cpu/ozone/rename_table.hh"
  41 #include "cpu/ozone/thread_state.hh"
  42 #include "mem/request.hh"
  43 #include "sim/eventq.hh"
  44
  45 template <class>
  46 class Checker;
  47 class ThreadContext;
  48
  49 template <class Impl>
  50 class OzoneThreadState;
  51
  52 template <class Impl>
  53 class LWBackEnd
  54 {
  55   public:
  56     typedef OzoneThreadState<Impl> Thread;
  57
  58     typedef typename Impl::Params Params;
  59     typedef typename Impl::DynInst DynInst;
  60     typedef typename Impl::DynInstPtr DynInstPtr;
  61     typedef typename Impl::FullCPU FullCPU;
  62     typedef typename Impl::FrontEnd FrontEnd;
  63     typedef typename Impl::FullCPU::CommStruct CommStruct;
  64
  65     struct SizeStruct {
  66         int size;
  67     };
  68
  69     typedef SizeStruct DispatchToIssue;
  70     typedef SizeStruct IssueToExec;
  71     typedef SizeStruct ExecToCommit;
  72     typedef SizeStruct Writeback;
  73
  74     TimeBuffer<DispatchToIssue> d2i;
  75     typename TimeBuffer<DispatchToIssue>::wire instsToDispatch;
  76     TimeBuffer<IssueToExec> i2e;
  77     typename TimeBuffer<IssueToExec>::wire instsToExecute;
  78     TimeBuffer<ExecToCommit> e2c;
  79     TimeBuffer<Writeback> numInstsToWB;
  80
  81     TimeBuffer<CommStruct> *comm;
  82     typename TimeBuffer<CommStruct>::wire toIEW;
  83     typename TimeBuffer<CommStruct>::wire fromCommit;
  84
  85     class TrapEvent : public Event {
  86       private:
  87         LWBackEnd<Impl> *be;
  88
  89       public:
  90         TrapEvent(LWBackEnd<Impl> *_be);
  91
  92         void process();
  93         const char *description();
  94     };
  95
  96     /** LdWriteback event for a load completion. */
  97     class LdWritebackEvent : public Event {
  98       private:
  99         /** Instruction that is writing back data to the register file. */
 100         DynInstPtr inst;
 101         /** Pointer to IEW stage. */
 102         LWBackEnd *be;
 103
 104         bool dcacheMiss;
 105
 106       public:
 107         /** Constructs a load writeback event. */
 108         LdWritebackEvent(DynInstPtr &_inst, LWBackEnd *be);
 109
 110         /** Processes writeback event. */
 111         virtual void process();
 112         /** Returns the description of the writeback event. */
 113         virtual const char *description();
 114
 115         void setDcacheMiss() { dcacheMiss = true; be->addDcacheMiss(inst); }
 116     };
 117
 118     LWBackEnd(Params *params);
 119
 120     std::string name() const;
 121
 122     void regStats();
 123
 124     void setCPU(FullCPU *cpu_ptr);
 125
 126     void setFrontEnd(FrontEnd *front_end_ptr)
 127     { frontEnd = front_end_ptr; }
 128
 129     void setTC(ThreadContext *tc_ptr)
 130     { tc = tc_ptr; }
 131
 132     void setThreadState(Thread *thread_ptr)
 133     { thread = thread_ptr; }
 134
 135     void setCommBuffer(TimeBuffer<CommStruct> *_comm);
 136
 137     void tick();
 138     void squash();
 139     void generateTCEvent() { tcSquash = true; }
 140     void squashFromTC();
 141     void squashFromTrap();
 142     void checkInterrupts();
 143     bool trapSquash;
 144     bool tcSquash;
 145
 146     template <class T>
 147     Fault read(RequestPtr req, T &data, int load_idx);
 148
 149     template <class T>
 150     Fault write(RequestPtr req, T &data, int store_idx);
 151
 152     Addr readCommitPC() { return commitPC; }
 153
 154     Addr commitPC;
 155
 156     Tick lastCommitCycle;
 157
 158     bool robEmpty() { return instList.empty(); }
 159
 160     bool isFull() { return numInsts >= numROBEntries; }
 161     bool isBlocked() { return status == Blocked || dispatchStatus == Blocked; }
 162
 163     void fetchFault(Fault &fault);
 164
 165     int wakeDependents(DynInstPtr &inst, bool memory_deps = false);
 166
 167     /** Tells memory dependence unit that a memory instruction needs to be
 168      * rescheduled. It will re-execute once replayMemInst() is called.
 169      */
 170     void rescheduleMemInst(DynInstPtr &inst);
 171
 172     /** Re-executes all rescheduled memory instructions. */
 173     void replayMemInst(DynInstPtr &inst);
 174
 175     /** Completes memory instruction. */
 176     void completeMemInst(DynInstPtr &inst) { }
 177
 178     void addDcacheMiss(DynInstPtr &inst)
 179     {
 180         waitingMemOps.insert(inst->seqNum);
 181         numWaitingMemOps++;
 182         DPRINTF(BE, "Adding a Dcache miss mem op [sn:%lli], total %i\n",
 183                 inst->seqNum, numWaitingMemOps);
 184     }
 185
 186     void removeDcacheMiss(DynInstPtr &inst)
 187     {
 188         assert(waitingMemOps.find(inst->seqNum) != waitingMemOps.end());
 189         waitingMemOps.erase(inst->seqNum);
 190         numWaitingMemOps--;
 191         DPRINTF(BE, "Removing a Dcache miss mem op [sn:%lli], total %i\n",
 192                 inst->seqNum, numWaitingMemOps);
 193     }
 194
 195     void addWaitingMemOp(DynInstPtr &inst)
 196     {
 197         waitingMemOps.insert(inst->seqNum);
 198         numWaitingMemOps++;
 199         DPRINTF(BE, "Adding a waiting mem op [sn:%lli], total %i\n",
 200                 inst->seqNum, numWaitingMemOps);
 201     }
 202
 203     void removeWaitingMemOp(DynInstPtr &inst)
 204     {
 205         assert(waitingMemOps.find(inst->seqNum) != waitingMemOps.end());
 206         waitingMemOps.erase(inst->seqNum);
 207         numWaitingMemOps--;
 208         DPRINTF(BE, "Removing a waiting mem op [sn:%lli], total %i\n",
 209                 inst->seqNum, numWaitingMemOps);
 210     }
 211
 212     void instToCommit(DynInstPtr &inst);
 213
 214     void switchOut();
 215     void doSwitchOut();
 216     void takeOverFrom(ThreadContext *old_tc = NULL);
 217
 218     bool isSwitchedOut() { return switchedOut; }
 219
 220   private:
 221     void generateTrapEvent(Tick latency = 0);
 222     void handleFault(Fault &fault, Tick latency = 0);
 223     void updateStructures();
 224     void dispatchInsts();
 225     void dispatchStall();
 226     void checkDispatchStatus();
 227     void executeInsts();
 228     void commitInsts();
 229     void addToLSQ(DynInstPtr &inst);
 230     void writebackInsts();
 231     bool commitInst(int inst_num);
 232     void squash(const InstSeqNum &sn);
 233     void squashDueToBranch(DynInstPtr &inst);
 234     void squashDueToMemViolation(DynInstPtr &inst);
 235     void squashDueToMemBlocked(DynInstPtr &inst);
 236     void updateExeInstStats(DynInstPtr &inst);
 237     void updateComInstStats(DynInstPtr &inst);
 238
 239   public:
 240     FullCPU *cpu;
 241
 242     FrontEnd *frontEnd;
 243
 244     ThreadContext *tc;
 245
 246     Thread *thread;
 247
 248     enum Status {
 249         Running,
 250         Idle,
 251         DcacheMissStall,
 252         DcacheMissComplete,
 253         Blocked,
 254         TrapPending
 255     };
 256
 257     Status status;
 258
 259     Status dispatchStatus;
 260
 261     Status commitStatus;
 262
 263     Counter funcExeInst;
 264
 265   private:
 266     typedef typename Impl::LdstQueue LdstQueue;
 267
 268     LdstQueue LSQ;
 269   public:
 270     RenameTable<Impl> commitRenameTable;
 271
 272     RenameTable<Impl> renameTable;
 273   private:
 274     class DCacheCompletionEvent : public Event
 275     {
 276       private:
 277         LWBackEnd *be;
 278
 279       public:
 280         DCacheCompletionEvent(LWBackEnd *_be);
 281
 282         virtual void process();
 283         virtual const char *description();
 284     };
 285
 286     friend class DCacheCompletionEvent;
 287
 288     DCacheCompletionEvent cacheCompletionEvent;
 289
 290     MemInterface *dcacheInterface;
 291
 292     // General back end width. Used if the more specific isn't given.
 293     int width;
 294
 295     // Dispatch width.
 296     int dispatchWidth;
 297     int numDispatchEntries;
 298     int dispatchSize;
 299
 300     int waitingInsts;
 301
 302     int issueWidth;
 303
 304     // Writeback width
 305     int wbWidth;
 306
 307     // Commit width
 308     int commitWidth;
 309
 310     /** Index into queue of instructions being written back. */
 311     unsigned wbNumInst;
 312
 313     /** Cycle number within the queue of instructions being written
 314      * back.  Used in case there are too many instructions writing
 315      * back at the current cycle and writesbacks need to be scheduled
 316      * for the future. See comments in instToCommit().
 317      */
 318     unsigned wbCycle;
 319
 320     int numROBEntries;
 321     int numInsts;
 322
 323     std::set<InstSeqNum> waitingMemOps;
 324     typedef std::set<InstSeqNum>::iterator MemIt;
 325     int numWaitingMemOps;
 326     unsigned maxOutstandingMemOps;
 327
 328     bool squashPending;
 329     InstSeqNum squashSeqNum;
 330     Addr squashNextPC;
 331
 332     Fault faultFromFetch;
 333     bool fetchHasFault;
 334
 335     bool switchedOut;
 336     bool switchPending;
 337
 338     DynInstPtr memBarrier;
 339
 340   private:
 341     struct pqCompare {
 342         bool operator() (const DynInstPtr &lhs, const DynInstPtr &rhs) const
 343         {
 344             return lhs->seqNum > rhs->seqNum;
 345         }
 346     };
 347
 348     typedef typename std::priority_queue<DynInstPtr, std::vector<DynInstPtr>, pqCompare> ReadyInstQueue;
 349     ReadyInstQueue exeList;
 350
 351     typedef typename std::list<DynInstPtr>::iterator InstListIt;
 352
 353     std::list<DynInstPtr> instList;
 354     std::list<DynInstPtr> waitingList;
 355     std::list<DynInstPtr> replayList;
 356     std::list<DynInstPtr> writeback;
 357
 358     int latency;
 359
 360     int squashLatency;
 361
 362     bool exactFullStall;
 363
 364     // number of cycles stalled for D-cache misses
 365 /*    Stats::Scalar<> dcacheStallCycles;
 366       Counter lastDcacheStall;
 367 */
 368     Stats::Vector<> rob_cap_events;
 369     Stats::Vector<> rob_cap_inst_count;
 370     Stats::Vector<> iq_cap_events;
 371     Stats::Vector<> iq_cap_inst_count;
 372     // total number of instructions executed
 373     Stats::Vector<> exe_inst;
 374     Stats::Vector<> exe_swp;
 375     Stats::Vector<> exe_nop;
 376     Stats::Vector<> exe_refs;
 377     Stats::Vector<> exe_loads;
 378     Stats::Vector<> exe_branches;
 379
 380     Stats::Vector<> issued_ops;
 381
 382     // total number of loads forwaded from LSQ stores
 383     Stats::Vector<> lsq_forw_loads;
 384
 385     // total number of loads ignored due to invalid addresses
 386     Stats::Vector<> inv_addr_loads;
 387
 388     // total number of software prefetches ignored due to invalid addresses
 389     Stats::Vector<> inv_addr_swpfs;
 390     // ready loads blocked due to memory disambiguation
 391     Stats::Vector<> lsq_blocked_loads;
 392
 393     Stats::Scalar<> lsqInversion;
 394
 395     Stats::Vector<> n_issued_dist;
 396     Stats::VectorDistribution<> issue_delay_dist;
 397
 398     Stats::VectorDistribution<> queue_res_dist;
 399 /*
 400     Stats::Vector<> stat_fu_busy;
 401     Stats::Vector2d<> stat_fuBusy;
 402     Stats::Vector<> dist_unissued;
 403     Stats::Vector2d<> stat_issued_inst_type;
 404
 405     Stats::Formula misspec_cnt;
 406     Stats::Formula misspec_ipc;
 407     Stats::Formula issue_rate;
 408     Stats::Formula issue_stores;
 409     Stats::Formula issue_op_rate;
 410     Stats::Formula fu_busy_rate;
 411     Stats::Formula commit_stores;
 412     Stats::Formula commit_ipc;
 413     Stats::Formula commit_ipb;
 414     Stats::Formula lsq_inv_rate;
 415 */
 416     Stats::Vector<> writeback_count;
 417     Stats::Vector<> producer_inst;
 418     Stats::Vector<> consumer_inst;
 419     Stats::Vector<> wb_penalized;
 420
 421     Stats::Formula wb_rate;
 422     Stats::Formula wb_fanout;
 423     Stats::Formula wb_penalized_rate;
 424
 425     // total number of instructions committed
 426     Stats::Vector<> stat_com_inst;
 427     Stats::Vector<> stat_com_swp;
 428     Stats::Vector<> stat_com_refs;
 429     Stats::Vector<> stat_com_loads;
 430     Stats::Vector<> stat_com_membars;
 431     Stats::Vector<> stat_com_branches;
 432
 433     Stats::Distribution<> n_committed_dist;
 434
 435     Stats::Scalar<> commit_eligible_samples;
 436     Stats::Vector<> commit_eligible;
 437
 438     Stats::Vector<> squashedInsts;
 439     Stats::Vector<> ROBSquashedInsts;
 440
 441     Stats::Scalar<> ROB_fcount;
 442     Stats::Formula ROB_full_rate;
 443
 444     Stats::Vector<>  ROB_count;  // cumulative ROB occupancy
 445     Stats::Formula ROB_occ_rate;
 446     Stats::VectorDistribution<> ROB_occ_dist;
 447   public:
 448     void dumpInsts();
 449
 450     Checker<DynInstPtr> *checker;
 451 };
 452
 453 template <class Impl>
 454 template <class T>
 455 Fault
 456 LWBackEnd<Impl>::read(RequestPtr req, T &data, int load_idx)
 457 {
 458     return LSQ.read(req, data, load_idx);
 459 }
 460
 461 template <class Impl>
 462 template <class T>
 463 Fault
 464 LWBackEnd<Impl>::write(RequestPtr req, T &data, int store_idx)
 465 {
 466     return LSQ.write(req, data, store_idx);
 467 }
 468
 469 #endif // __CPU_OZONE_LW_BACK_END_HH__