2 * Copyright (c) 2006 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "config/use_checker.hh"
33 #include "cpu/ozone/lw_back_end.hh"
34 #include "cpu/op_class.hh"
37 #include "cpu/checker/cpu.hh"
42 LWBackEnd<Impl>::generateTrapEvent(Tick latency)
44 DPRINTF(BE, "Generating trap event\n");
46 TrapEvent *trap = new TrapEvent(this);
48 trap->schedule(curTick + cpu->cycles(latency));
50 thread->trapPending = true;
55 LWBackEnd<Impl>::wakeDependents(DynInstPtr &inst, bool memory_deps)
57 assert(!inst->isSquashed());
58 std::vector<DynInstPtr> &dependents = memory_deps ? inst->getMemDeps() :
59 inst->getDependents();
60 int num_outputs = dependents.size();
62 DPRINTF(BE, "Waking instruction [sn:%lli] dependents in IQ\n", inst->seqNum);
64 for (int i = 0; i < num_outputs; i++) {
65 DynInstPtr dep_inst = dependents[i];
67 dep_inst->markSrcRegReady();
69 if (!dep_inst->isSquashed())
70 dep_inst->markMemInstReady(inst.get());
73 DPRINTF(BE, "Marking source reg ready [sn:%lli] in IQ\n", dep_inst->seqNum);
75 if (dep_inst->readyToIssue() && dep_inst->isInROB() &&
76 !dep_inst->isNonSpeculative() && !dep_inst->isStoreConditional() &&
77 dep_inst->memDepReady() && !dep_inst->isMemBarrier() &&
78 !dep_inst->isWriteBarrier()) {
79 DPRINTF(BE, "Adding instruction to exeList [sn:%lli]\n",
81 exeList.push(dep_inst);
82 if (dep_inst->iqItValid) {
83 DPRINTF(BE, "Removing instruction from waiting list\n");
84 waitingList.erase(dep_inst->iqIt);
86 dep_inst->iqItValid = false;
87 assert(waitingInsts >= 0);
89 if (dep_inst->isMemRef()) {
90 removeWaitingMemOp(dep_inst);
91 DPRINTF(BE, "Issued a waiting mem op [sn:%lli]\n",
101 LWBackEnd<Impl>::rescheduleMemInst(DynInstPtr &inst)
103 replayList.push_front(inst);
106 template <class Impl>
107 LWBackEnd<Impl>::TrapEvent::TrapEvent(LWBackEnd<Impl> *_be)
108 : Event(&mainEventQueue, CPU_Tick_Pri), be(_be)
110 this->setFlags(Event::AutoDelete);
113 template <class Impl>
115 LWBackEnd<Impl>::TrapEvent::process()
117 be->trapSquash = true;
120 template <class Impl>
122 LWBackEnd<Impl>::TrapEvent::description()
127 template <class Impl>
129 LWBackEnd<Impl>::replayMemInst(DynInstPtr &inst)
131 bool found_inst = false;
132 while (!replayList.empty()) {
133 exeList.push(replayList.front());
134 if (replayList.front() == inst) {
137 replayList.pop_front();
142 template <class Impl>
143 LWBackEnd<Impl>::LWBackEnd(Params *params)
144 : d2i(5, 5), i2e(5, 5), e2c(5, 5), numInstsToWB(5, 5),
145 trapSquash(false), tcSquash(false),
146 width(params->backEndWidth), exactFullStall(true)
148 numROBEntries = params->numROBEntries;
150 numDispatchEntries = 32;
151 maxOutstandingMemOps = params->maxOutstandingMemOps;
152 numWaitingMemOps = 0;
155 switchPending = false;
159 // Setup IQ and LSQ with their parameters here.
160 instsToDispatch = d2i.getWire(-1);
162 instsToExecute = i2e.getWire(-1);
164 dispatchWidth = params->dispatchWidth ? params->dispatchWidth : width;
165 issueWidth = params->issueWidth ? params->issueWidth : width;
166 wbWidth = params->wbWidth ? params->wbWidth : width;
167 commitWidth = params->commitWidth ? params->commitWidth : width;
169 LSQ.init(params, params->LQEntries, params->SQEntries, 0);
171 dispatchStatus = Running;
174 template <class Impl>
176 LWBackEnd<Impl>::name() const
178 return cpu->name() + ".backend";
181 template <class Impl>
183 LWBackEnd<Impl>::regStats()
185 using namespace Stats;
187 .init(cpu->number_of_threads)
188 .name(name() + ".ROB:cap_events")
189 .desc("number of cycles where ROB cap was active")
194 .init(cpu->number_of_threads)
195 .name(name() + ".ROB:cap_inst")
196 .desc("number of instructions held up by ROB cap")
201 .init(cpu->number_of_threads)
202 .name(name() +".IQ:cap_events" )
203 .desc("number of cycles where IQ cap was active")
208 .init(cpu->number_of_threads)
209 .name(name() + ".IQ:cap_inst")
210 .desc("number of instructions held up by IQ cap")
216 .init(cpu->number_of_threads)
217 .name(name() + ".ISSUE:count")
218 .desc("number of insts issued")
223 .init(cpu->number_of_threads)
224 .name(name() + ".ISSUE:swp")
225 .desc("number of swp insts issued")
230 .init(cpu->number_of_threads)
231 .name(name() + ".ISSUE:nop")
232 .desc("number of nop insts issued")
237 .init(cpu->number_of_threads)
238 .name(name() + ".ISSUE:refs")
239 .desc("number of memory reference insts issued")
244 .init(cpu->number_of_threads)
245 .name(name() + ".ISSUE:loads")
246 .desc("number of load insts issued")
251 .init(cpu->number_of_threads)
252 .name(name() + ".ISSUE:branches")
253 .desc("Number of branches issued")
258 .init(cpu->number_of_threads)
259 .name(name() + ".ISSUE:op_count")
260 .desc("number of insts issued")
265 for (int i=0; i<Num_OpClasses; ++i) {
266 stringstream subname;
267 subname << opClassStrings[i] << "_delay";
268 issue_delay_dist.subname(i, subname.str());
275 .init(cpu->number_of_threads)
276 .name(name() + ".LSQ:forw_loads")
277 .desc("number of loads forwarded via LSQ")
282 .init(cpu->number_of_threads)
283 .name(name() + ".ISSUE:addr_loads")
284 .desc("number of invalid-address loads")
289 .init(cpu->number_of_threads)
290 .name(name() + ".ISSUE:addr_swpfs")
291 .desc("number of invalid-address SW prefetches")
296 .init(cpu->number_of_threads)
297 .name(name() + ".LSQ:blocked_loads")
298 .desc("number of ready loads not issued due to memory disambiguation")
303 .name(name() + ".ISSUE:lsq_invert")
304 .desc("Number of times LSQ instruction issued early")
308 .init(issueWidth + 1)
309 .name(name() + ".ISSUE:issued_per_cycle")
310 .desc("Number of insts issued each cycle")
311 .flags(total | pdf | dist)
314 .init(Num_OpClasses,0,99,2)
315 .name(name() + ".ISSUE:")
316 .desc("cycles from operands ready to issue")
321 .init(Num_OpClasses, 0, 99, 2)
322 .name(name() + ".IQ:residence:")
323 .desc("cycles from dispatch to issue")
324 .flags(total | pdf | cdf )
326 for (int i = 0; i < Num_OpClasses; ++i) {
327 queue_res_dist.subname(i, opClassStrings[i]);
331 .init(cpu->number_of_threads)
332 .name(name() + ".WB:count")
333 .desc("cumulative count of insts written-back")
338 .init(cpu->number_of_threads)
339 .name(name() + ".WB:producers")
340 .desc("num instructions producing a value")
345 .init(cpu->number_of_threads)
346 .name(name() + ".WB:consumers")
347 .desc("num instructions consuming a value")
352 .init(cpu->number_of_threads)
353 .name(name() + ".WB:penalized")
354 .desc("number of instrctions required to write to 'other' IQ")
360 .name(name() + ".WB:penalized_rate")
361 .desc ("fraction of instructions written-back that wrote to 'other' IQ")
365 wb_penalized_rate = wb_penalized / writeback_count;
368 .name(name() + ".WB:fanout")
369 .desc("average fanout of values written-back")
373 wb_fanout = producer_inst / consumer_inst;
376 .name(name() + ".WB:rate")
377 .desc("insts written-back per cycle")
380 wb_rate = writeback_count / cpu->numCycles;
383 .init(cpu->number_of_threads)
384 .name(name() + ".COM:count")
385 .desc("Number of instructions committed")
390 .init(cpu->number_of_threads)
391 .name(name() + ".COM:swp_count")
392 .desc("Number of s/w prefetches committed")
397 .init(cpu->number_of_threads)
398 .name(name() + ".COM:refs")
399 .desc("Number of memory references committed")
404 .init(cpu->number_of_threads)
405 .name(name() + ".COM:loads")
406 .desc("Number of loads committed")
411 .init(cpu->number_of_threads)
412 .name(name() + ".COM:membars")
413 .desc("Number of memory barriers committed")
418 .init(cpu->number_of_threads)
419 .name(name() + ".COM:branches")
420 .desc("Number of branches committed")
424 .init(0,commitWidth,1)
425 .name(name() + ".COM:committed_per_cycle")
426 .desc("Number of insts commited each cycle")
431 // Commit-Eligible instructions...
433 // -> The number of instructions eligible to commit in those
434 // cycles where we reached our commit BW limit (less the number
435 // actually committed)
437 // -> The average value is computed over ALL CYCLES... not just
438 // the BW limited cycles
440 // -> The standard deviation is computed only over cycles where
441 // we reached the BW limit
444 .init(cpu->number_of_threads)
445 .name(name() + ".COM:bw_limited")
446 .desc("number of insts not committed due to BW limits")
450 commit_eligible_samples
451 .name(name() + ".COM:bw_lim_events")
452 .desc("number cycles where commit BW limit reached")
456 .init(cpu->number_of_threads)
457 .name(name() + ".COM:squashed_insts")
458 .desc("Number of instructions removed from inst list")
462 .init(cpu->number_of_threads)
463 .name(name() + ".COM:rob_squashed_insts")
464 .desc("Number of instructions removed from inst list when they reached the head of the ROB")
468 .name(name() + ".ROB:full_count")
469 .desc("number of cycles where ROB was full")
473 .init(cpu->number_of_threads)
474 .name(name() + ".ROB:occupancy")
475 .desc(name() + ".ROB occupancy (cumulative)")
480 .name(name() + ".ROB:full_rate")
481 .desc("ROB full per cycle")
483 ROB_full_rate = ROB_fcount / cpu->numCycles;
486 .name(name() + ".ROB:occ_rate")
487 .desc("ROB occupancy rate")
490 ROB_occ_rate = ROB_count / cpu->numCycles;
493 .init(cpu->number_of_threads,0,numROBEntries,2)
494 .name(name() + ".ROB:occ_dist")
495 .desc("ROB Occupancy per cycle")
500 template <class Impl>
502 LWBackEnd<Impl>::setCPU(OzoneCPU *cpu_ptr)
506 checker = cpu->checker;
509 template <class Impl>
511 LWBackEnd<Impl>::setCommBuffer(TimeBuffer<CommStruct> *_comm)
514 toIEW = comm->getWire(0);
515 fromCommit = comm->getWire(-1);
519 template <class Impl>
521 LWBackEnd<Impl>::checkInterrupts()
523 if (cpu->checkInterrupts &&
524 cpu->check_interrupts() &&
525 !cpu->inPalMode(thread->readPC()) &&
528 frontEnd->interruptPending = true;
529 if (robEmpty() && !LSQ.hasStoresToWB()) {
530 // Will need to squash all instructions currently in flight and have
531 // the interrupt handler restart at the last non-committed inst.
532 // Most of that can be handled through the trap() function. The
533 // processInterrupts() function really just checks for interrupts
534 // and then calls trap() if there is an interrupt present.
536 // Not sure which thread should be the one to interrupt. For now
537 // always do thread 0.
538 assert(!thread->inSyscall);
539 thread->inSyscall = true;
541 // CPU will handle implementation of the interrupt.
542 cpu->processInterrupts();
544 // Now squash or record that I need to squash this cycle.
545 commitStatus = TrapPending;
547 // Exit state update mode to avoid accidental updating.
548 thread->inSyscall = false;
550 // Generate trap squash event.
553 DPRINTF(BE, "Interrupt detected.\n");
555 DPRINTF(BE, "Interrupt must wait for ROB to drain.\n");
560 template <class Impl>
562 LWBackEnd<Impl>::handleFault(Fault &fault, Tick latency)
564 DPRINTF(BE, "Handling fault!\n");
566 assert(!thread->inSyscall);
568 thread->inSyscall = true;
570 // Consider holding onto the trap and waiting until the trap event
571 // happens for this to be executed.
572 fault->invoke(thread->getTC());
574 // Exit state update mode to avoid accidental updating.
575 thread->inSyscall = false;
577 commitStatus = TrapPending;
579 // Generate trap squash event.
580 generateTrapEvent(latency);
584 template <class Impl>
586 LWBackEnd<Impl>::tick()
588 DPRINTF(BE, "Ticking back end\n");
590 if (switchPending && robEmpty() && !LSQ.hasStoresToWB()) {
591 cpu->signalSwitched();
595 ROB_count[0]+= numInsts;
599 // Read in any done instruction information and update the IQ or LSQ.
608 } else if (tcSquash) {
613 if (dispatchStatus != Blocked) {
616 checkDispatchStatus();
619 if (commitStatus != TrapPending) {
625 LSQ.writebackStores();
627 DPRINTF(BE, "Waiting insts: %i, mem ops: %i, ROB entries in use: %i, "
628 "LSQ loads: %i, LSQ stores: %i\n",
629 waitingInsts, numWaitingMemOps, numInsts,
630 LSQ.numLoads(), LSQ.numStores());
633 assert(numInsts == instList.size());
634 assert(waitingInsts == waitingList.size());
635 assert(numWaitingMemOps == waitingMemOps.size());
636 assert(!switchedOut);
640 template <class Impl>
642 LWBackEnd<Impl>::updateStructures()
644 if (fromCommit->doneSeqNum) {
645 LSQ.commitLoads(fromCommit->doneSeqNum);
646 LSQ.commitStores(fromCommit->doneSeqNum);
649 if (fromCommit->nonSpecSeqNum) {
650 if (fromCommit->uncached) {
651 // LSQ.executeLoad(fromCommit->lqIdx);
653 // IQ.scheduleNonSpec(
654 // fromCommit->nonSpecSeqNum);
659 template <class Impl>
661 LWBackEnd<Impl>::addToLSQ(DynInstPtr &inst)
663 // Do anything LSQ specific here?
667 template <class Impl>
669 LWBackEnd<Impl>::dispatchInsts()
671 DPRINTF(BE, "Trying to dispatch instructions.\n");
673 while (numInsts < numROBEntries &&
674 numWaitingMemOps < maxOutstandingMemOps) {
675 // Get instruction from front of time buffer
676 DynInstPtr inst = frontEnd->getInst();
679 } else if (inst->isSquashed()) {
684 instList.push_front(inst);
688 DPRINTF(BE, "Dispatching instruction [sn:%lli] PC:%#x\n",
689 inst->seqNum, inst->readPC());
691 for (int i = 0; i < inst->numDestRegs(); ++i)
692 renameTable[inst->destRegIdx(i)] = inst;
694 if (inst->isMemBarrier() || inst->isWriteBarrier()) {
696 DPRINTF(BE, "Instruction [sn:%lli] is waiting on "
697 "barrier [sn:%lli].\n",
698 inst->seqNum, memBarrier->seqNum);
699 memBarrier->addMemDependent(inst);
700 inst->addSrcMemInst(memBarrier);
703 inst->setCanCommit();
704 } else if (inst->readyToIssue() &&
705 !inst->isNonSpeculative() &&
706 !inst->isStoreConditional()) {
707 if (inst->isMemRef()) {
711 DPRINTF(BE, "Instruction [sn:%lli] is waiting on "
712 "barrier [sn:%lli].\n",
713 inst->seqNum, memBarrier->seqNum);
714 memBarrier->addMemDependent(inst);
715 inst->addSrcMemInst(memBarrier);
716 addWaitingMemOp(inst);
718 waitingList.push_front(inst);
719 inst->iqIt = waitingList.begin();
720 inst->iqItValid = true;
723 DPRINTF(BE, "Instruction [sn:%lli] ready, addding to "
728 } else if (inst->isNop()) {
729 DPRINTF(BE, "Nop encountered [sn:%lli], skipping exeList.\n",
733 inst->setCanCommit();
735 DPRINTF(BE, "Instruction [sn:%lli] ready, addding to "
741 if (inst->isNonSpeculative() || inst->isStoreConditional()) {
742 inst->setCanCommit();
743 DPRINTF(BE, "Adding non speculative instruction\n");
746 if (inst->isMemRef()) {
747 addWaitingMemOp(inst);
750 memBarrier->addMemDependent(inst);
751 inst->addSrcMemInst(memBarrier);
753 DPRINTF(BE, "Instruction [sn:%lli] is waiting on "
754 "barrier [sn:%lli].\n",
755 inst->seqNum, memBarrier->seqNum);
759 DPRINTF(BE, "Instruction [sn:%lli] not ready, addding to "
762 waitingList.push_front(inst);
763 inst->iqIt = waitingList.begin();
764 inst->iqItValid = true;
769 // Check if IQ or LSQ is full. If so we'll need to break and stop
770 // removing instructions. Also update the number of insts to remove
771 // from the queue. Check here if we don't care about exact stall
776 DPRINTF(BE, "IQ is full!\n");
778 } else if (LSQ.isFull()) {
779 DPRINTF(BE, "LSQ is full!\n");
781 } else if (isFull()) {
782 DPRINTF(BE, "ROB is full!\n");
794 template <class Impl>
796 LWBackEnd<Impl>::dispatchStall()
798 dispatchStatus = Blocked;
799 if (!cpu->decoupledFrontEnd) {
800 // Tell front end to stall here through a timebuffer, or just tell
805 template <class Impl>
807 LWBackEnd<Impl>::checkDispatchStatus()
809 DPRINTF(BE, "Checking dispatch status\n");
810 assert(dispatchStatus == Blocked);
811 if (!LSQ.isFull() && !isFull()) {
812 DPRINTF(BE, "Dispatch no longer blocked\n");
813 dispatchStatus = Running;
818 template <class Impl>
820 LWBackEnd<Impl>::executeInsts()
822 DPRINTF(BE, "Trying to execute instructions\n");
824 int num_executed = 0;
825 while (!exeList.empty() && num_executed < issueWidth) {
826 DynInstPtr inst = exeList.top();
828 DPRINTF(BE, "Executing inst [sn:%lli] PC: %#x\n",
829 inst->seqNum, inst->readPC());
831 // Check if the instruction is squashed; if so then skip it
832 // and don't count it towards the FU usage.
833 if (inst->isSquashed()) {
834 DPRINTF(BE, "Execute: Instruction was squashed.\n");
836 // Not sure how to handle this plus the method of sending # of
837 // instructions to use. Probably will just have to count it
838 // towards the bandwidth usage, but not the FU usage.
841 // Consider this instruction executed so that commit can go
842 // ahead and retire the instruction.
845 // Not sure if I should set this here or just let commit try to
846 // commit any squashed instructions. I like the latter a bit more.
847 inst->setCanCommit();
849 // ++iewExecSquashedInsts;
855 Fault fault = NoFault;
857 // Execute instruction.
858 // Note that if the instruction faults, it will be handled
859 // at the commit stage.
860 if (inst->isMemRef() &&
861 (!inst->isDataPrefetch() && !inst->isInstPrefetch())) {
862 DPRINTF(BE, "Execute: Initiating access for memory "
865 if (inst->isLoad()) {
866 LSQ.executeLoad(inst);
867 } else if (inst->isStore()) {
868 LSQ.executeStore(inst);
869 if (inst->req && !(inst->req->getFlags() & LOCKED)) {
875 panic("Unknown mem type!");
885 updateExeInstStats(inst);
892 if (inst->mispredicted()) {
893 squashDueToBranch(inst);
895 } else if (LSQ.violation()) {
896 // Get the DynInst that caused the violation. Note that this
897 // clears the violation signal.
899 violator = LSQ.getMemDepViolator();
901 DPRINTF(BE, "LDSTQ detected a violation. Violator PC: "
902 "%#x, inst PC: %#x. Addr is: %#x.\n",
903 violator->readPC(), inst->readPC(), inst->physEffAddr);
906 squashDueToMemViolation(inst);
910 issued_ops[0]+= num_executed;
911 n_issued_dist[num_executed]++;
916 LWBackEnd<Impl>::instToCommit(DynInstPtr &inst)
919 DPRINTF(BE, "Sending instructions to commit [sn:%lli] PC %#x.\n",
920 inst->seqNum, inst->readPC());
922 if (!inst->isSquashed()) {
923 DPRINTF(BE, "Writing back instruction [sn:%lli] PC %#x.\n",
924 inst->seqNum, inst->readPC());
926 inst->setCanCommit();
928 if (inst->isExecuted()) {
929 inst->setResultReady();
930 int dependents = wakeDependents(inst);
933 consumer_inst[0]+= dependents;
938 writeback_count[0]++;
941 template <class Impl>
943 LWBackEnd<Impl>::writebackInsts()
945 int wb_width = wbWidth;
946 // Using this method I'm not quite sure how to prevent an
947 // instruction from waking its own dependents multiple times,
948 // without the guarantee that commit always has enough bandwidth
949 // to accept all instructions being written back. This guarantee
950 // might not be too unrealistic.
951 InstListIt wb_inst_it = writeback.begin();
952 InstListIt wb_end_it = writeback.end();
954 int consumer_insts = 0;
956 for (; inst_num < wb_width &&
957 wb_inst_it != wb_end_it; inst_num++) {
958 DynInstPtr inst = (*wb_inst_it);
960 // Some instructions will be sent to commit without having
961 // executed because they need commit to handle them.
962 // E.g. Uncached loads have not actually executed when they
963 // are first sent to commit. Instead commit must tell the LSQ
964 // when it's ready to execute the uncached load.
965 if (!inst->isSquashed()) {
966 DPRINTF(BE, "Writing back instruction [sn:%lli] PC %#x.\n",
967 inst->seqNum, inst->readPC());
969 inst->setCanCommit();
970 inst->setResultReady();
972 if (inst->isExecuted()) {
973 int dependents = wakeDependents(inst);
976 consumer_insts+= dependents;
981 writeback.erase(wb_inst_it++);
983 LSQ.writebackStores();
984 consumer_inst[0]+= consumer_insts;
985 writeback_count[0]+= inst_num;
988 template <class Impl>
990 LWBackEnd<Impl>::commitInst(int inst_num)
992 // Read instruction from the head of the ROB
993 DynInstPtr inst = instList.back();
995 // Make sure instruction is valid
998 if (!inst->readyToCommit())
1001 DPRINTF(BE, "Trying to commit instruction [sn:%lli] PC:%#x\n",
1002 inst->seqNum, inst->readPC());
1004 thread->setPC(inst->readPC());
1005 thread->setNextPC(inst->readNextPC());
1006 inst->setAtCommit();
1008 // If the instruction is not executed yet, then it is a non-speculative
1009 // or store inst. Signal backwards that it should be executed.
1010 if (!inst->isExecuted()) {
1011 if (inst->isNonSpeculative() ||
1012 inst->isStoreConditional() ||
1013 inst->isMemBarrier() ||
1014 inst->isWriteBarrier()) {
1016 // Hack to make sure syscalls aren't executed until all stores
1017 // write back their data. This direct communication shouldn't
1018 // be used for anything other than this.
1019 if (inst_num > 0 || LSQ.hasStoresToWB())
1021 if ((inst->isMemBarrier() || inst->isWriteBarrier() ||
1022 inst->isQuiesce()) &&
1023 LSQ.hasStoresToWB())
1026 DPRINTF(BE, "Waiting for all stores to writeback.\n");
1030 DPRINTF(BE, "Encountered a store or non-speculative "
1031 "instruction at the head of the ROB, PC %#x.\n",
1034 if (inst->isMemBarrier() || inst->isWriteBarrier()) {
1035 DPRINTF(BE, "Waking dependents on barrier [sn:%lli]\n",
1038 wakeDependents(inst, true);
1039 if (memBarrier == inst)
1041 inst->clearMemDependents();
1044 // Send back the non-speculative instruction's sequence number.
1045 if (inst->iqItValid) {
1046 DPRINTF(BE, "Removing instruction from waiting list\n");
1047 waitingList.erase(inst->iqIt);
1048 inst->iqItValid = false;
1050 assert(waitingInsts >= 0);
1051 if (inst->isStore())
1052 removeWaitingMemOp(inst);
1057 // Change the instruction so it won't try to commit again until
1059 inst->clearCanCommit();
1061 // ++commitNonSpecStalls;
1064 } else if (inst->isLoad()) {
1065 DPRINTF(BE, "[sn:%lli]: Uncached load, PC %#x.\n",
1066 inst->seqNum, inst->readPC());
1068 // Send back the non-speculative instruction's sequence
1069 // number. Maybe just tell the lsq to re-execute the load.
1071 // Send back the non-speculative instruction's sequence number.
1072 if (inst->iqItValid) {
1073 DPRINTF(BE, "Removing instruction from waiting list\n");
1074 waitingList.erase(inst->iqIt);
1075 inst->iqItValid = false;
1077 assert(waitingInsts >= 0);
1078 removeWaitingMemOp(inst);
1080 replayMemInst(inst);
1082 inst->clearCanCommit();
1086 panic("Trying to commit un-executed instruction "
1087 "of unknown type!\n");
1091 // Not handled for now.
1092 assert(!inst->isThreadSync());
1093 assert(inst->memDepReady());
1094 // Stores will mark themselves as totally completed as they need
1095 // to wait to writeback to memory. @todo: Hack...attempt to fix
1096 // having the checker be forced to wait until a store completes in
1097 // order to check all of the instructions. If the store at the
1098 // head of the check list misses, but a later store hits, then
1099 // loads in the checker may see the younger store values instead
1100 // of the store they should see. Either the checker needs its own
1101 // memory (annoying to update), its own store buffer (how to tell
1102 // which value is correct?), or something else...
1103 if (!inst->isStore()) {
1104 inst->setCompleted();
1106 // Check if the instruction caused a fault. If so, trap.
1107 Fault inst_fault = inst->getFault();
1109 // Use checker prior to updating anything due to traps or PC
1113 checker->verify(inst);
1117 if (inst_fault != NoFault) {
1118 DPRINTF(BE, "Inst [sn:%lli] PC %#x has a fault\n",
1119 inst->seqNum, inst->readPC());
1121 // Instruction is completed as it has a fault.
1122 inst->setCompleted();
1124 if (LSQ.hasStoresToWB()) {
1125 DPRINTF(BE, "Stores still in flight, will wait until drained.\n");
1127 } else if (inst_num != 0) {
1128 DPRINTF(BE, "Will wait until instruction is head of commit group.\n");
1132 else if (checker && inst->isStore()) {
1133 checker->verify(inst);
1138 static_cast<TheISA::MachInst>(inst->staticInst->machInst));
1140 handleFault(inst_fault);
1142 #else // !FULL_SYSTEM
1143 panic("fault (%d) detected @ PC %08p", inst_fault,
1145 #endif // FULL_SYSTEM
1150 for (int i = 0; i < inst->numDestRegs(); ++i) {
1151 DPRINTF(BE, "Commit rename map setting reg %i to [sn:%lli]\n",
1152 (int)inst->destRegIdx(i), inst->seqNum);
1153 thread->renameTable[inst->destRegIdx(i)] = inst;
1157 if (inst->traceData) {
1158 inst->traceData->setFetchSeq(inst->seqNum);
1159 inst->traceData->setCPSeq(thread->numInst);
1160 inst->traceData->finalize();
1161 inst->traceData = NULL;
1164 inst->clearDependents();
1166 frontEnd->addFreeRegs(freed_regs);
1168 instList.pop_back();
1171 ++thread->funcExeInst;
1172 // Maybe move this to where the fault is handled; if the fault is
1173 // handled, don't try to set this myself as the fault will set it.
1174 // If not, then I set thread->PC = thread->nextPC and
1175 // thread->nextPC = thread->nextPC + 4.
1176 thread->setPC(thread->readNextPC());
1177 thread->setNextPC(thread->readNextPC() + sizeof(TheISA::MachInst));
1178 updateComInstStats(inst);
1180 // Write the done sequence number here.
1181 toIEW->doneSeqNum = inst->seqNum;
1182 lastCommitCycle = curTick;
1189 assert(!thread->inSyscall && !thread->trapPending);
1190 oldpc = thread->readPC();
1191 cpu->system->pcEventQueue.service(
1194 } while (oldpc != thread->readPC());
1196 DPRINTF(BE, "PC skip function event, stopping commit\n");
1204 template <class Impl>
1206 LWBackEnd<Impl>::commitInsts()
1208 // Not sure this should be a loop or not.
1210 while (!instList.empty() && inst_num < commitWidth) {
1211 if (instList.back()->isSquashed()) {
1212 instList.back()->clearDependents();
1213 instList.pop_back();
1215 ROBSquashedInsts[instList.back()->threadNumber]++;
1219 if (!commitInst(inst_num++)) {
1220 DPRINTF(BE, "Can't commit, Instruction [sn:%lli] PC "
1221 "%#x is head of ROB and not ready\n",
1222 instList.back()->seqNum, instList.back()->readPC());
1227 n_committed_dist.sample(inst_num);
1230 template <class Impl>
1232 LWBackEnd<Impl>::squash(const InstSeqNum &sn)
1237 InstListIt waiting_list_end = waitingList.end();
1238 InstListIt insts_it = waitingList.begin();
1240 while (insts_it != waiting_list_end && (*insts_it)->seqNum > sn)
1242 if ((*insts_it)->isSquashed()) {
1246 DPRINTF(BE, "Squashing instruction on waitingList PC %#x, [sn:%lli].\n",
1247 (*insts_it)->readPC(),
1248 (*insts_it)->seqNum);
1250 if ((*insts_it)->isMemRef()) {
1251 DPRINTF(BE, "Squashing a waiting mem op [sn:%lli]\n",
1252 (*insts_it)->seqNum);
1253 removeWaitingMemOp((*insts_it));
1256 waitingList.erase(insts_it++);
1259 assert(waitingInsts >= 0);
1261 insts_it = instList.begin();
1263 while (!instList.empty() && (*insts_it)->seqNum > sn)
1265 if ((*insts_it)->isSquashed()) {
1269 DPRINTF(BE, "Squashing instruction on inst list PC %#x, [sn:%lli].\n",
1270 (*insts_it)->readPC(),
1271 (*insts_it)->seqNum);
1273 // Mark the instruction as squashed, and ready to commit so that
1274 // it can drain out of the pipeline.
1275 (*insts_it)->setSquashed();
1277 (*insts_it)->setCanCommit();
1279 (*insts_it)->clearInROB();
1281 for (int i = 0; i < (*insts_it)->numDestRegs(); ++i) {
1282 DynInstPtr prev_dest = (*insts_it)->getPrevDestInst(i);
1283 DPRINTF(BE, "Commit rename map setting reg %i to [sn:%lli]\n",
1284 (int)(*insts_it)->destRegIdx(i), prev_dest->seqNum);
1285 renameTable[(*insts_it)->destRegIdx(i)] = prev_dest;
1289 (*insts_it)->clearDependents();
1291 squashedInsts[(*insts_it)->threadNumber]++;
1293 instList.erase(insts_it++);
1297 insts_it = waitingList.begin();
1298 while (!waitingList.empty() && insts_it != waitingList.end()) {
1299 if ((*insts_it)->seqNum < sn) {
1303 assert((*insts_it)->isSquashed());
1305 waitingList.erase(insts_it++);
1309 while (memBarrier && memBarrier->seqNum > sn) {
1310 DPRINTF(BE, "[sn:%lli] Memory barrier squashed (or previously "
1311 "squashed)\n", memBarrier->seqNum);
1312 memBarrier->clearMemDependents();
1313 if (memBarrier->memDepReady()) {
1314 DPRINTF(BE, "No previous barrier\n");
1317 std::list<DynInstPtr> &srcs = memBarrier->getMemSrcs();
1318 memBarrier = srcs.front();
1320 assert(srcs.empty());
1321 DPRINTF(BE, "Previous barrier: [sn:%lli]\n",
1322 memBarrier->seqNum);
1326 frontEnd->addFreeRegs(freed_regs);
1329 template <class Impl>
1331 LWBackEnd<Impl>::squashFromTC()
1333 InstSeqNum squashed_inst = robEmpty() ? 0 : instList.back()->seqNum - 1;
1334 squash(squashed_inst);
1335 frontEnd->squash(squashed_inst, thread->readPC(),
1337 frontEnd->interruptPending = false;
1339 thread->trapPending = false;
1340 thread->inSyscall = false;
1342 commitStatus = Running;
1345 template <class Impl>
1347 LWBackEnd<Impl>::squashFromTrap()
1349 InstSeqNum squashed_inst = robEmpty() ? 0 : instList.back()->seqNum - 1;
1350 squash(squashed_inst);
1351 frontEnd->squash(squashed_inst, thread->readPC(),
1353 frontEnd->interruptPending = false;
1355 thread->trapPending = false;
1356 thread->inSyscall = false;
1358 commitStatus = Running;
1361 template <class Impl>
1363 LWBackEnd<Impl>::squashDueToBranch(DynInstPtr &inst)
1365 // Update the branch predictor state I guess
1366 DPRINTF(BE, "Squashing due to branch [sn:%lli], will restart at PC %#x\n",
1367 inst->seqNum, inst->readNextPC());
1368 squash(inst->seqNum);
1369 frontEnd->squash(inst->seqNum, inst->readNextPC(),
1370 true, inst->mispredicted());
1373 template <class Impl>
1375 LWBackEnd<Impl>::squashDueToMemViolation(DynInstPtr &inst)
1377 // Update the branch predictor state I guess
1378 DPRINTF(BE, "Squashing due to violation [sn:%lli], will restart at PC %#x\n",
1379 inst->seqNum, inst->readNextPC());
1380 squash(inst->seqNum);
1381 frontEnd->squash(inst->seqNum, inst->readNextPC(),
1382 false, inst->mispredicted());
1385 template <class Impl>
1387 LWBackEnd<Impl>::squashDueToMemBlocked(DynInstPtr &inst)
1389 DPRINTF(IEW, "Memory blocked, squashing load and younger insts, "
1390 "PC: %#x [sn:%i].\n", inst->readPC(), inst->seqNum);
1392 squash(inst->seqNum - 1);
1393 frontEnd->squash(inst->seqNum - 1, inst->readPC());
1396 template <class Impl>
1398 LWBackEnd<Impl>::fetchFault(Fault &fault)
1400 faultFromFetch = fault;
1401 fetchHasFault = true;
1404 template <class Impl>
1406 LWBackEnd<Impl>::switchOut()
1408 switchPending = true;
1411 template <class Impl>
1413 LWBackEnd<Impl>::doSwitchOut()
1416 switchPending = false;
1417 // Need to get rid of all committed, non-speculative state and write it
1418 // to memory/TC. In this case this is stores that have committed and not
1419 // yet written back.
1421 assert(!LSQ.hasStoresToWB());
1428 template <class Impl>
1430 LWBackEnd<Impl>::takeOverFrom(ThreadContext *old_tc)
1432 switchedOut = false;
1437 numWaitingMemOps = 0;
1438 waitingMemOps.clear();
1440 switchedOut = false;
1441 dispatchStatus = Running;
1442 commitStatus = Running;
1443 LSQ.takeOverFrom(old_tc);
1446 template <class Impl>
1448 LWBackEnd<Impl>::updateExeInstStats(DynInstPtr &inst)
1450 int thread_number = inst->threadNumber;
1453 // Pick off the software prefetches
1456 if (inst->isDataPrefetch())
1457 exe_swp[thread_number]++;
1459 exe_inst[thread_number]++;
1461 exe_inst[thread_number]++;
1465 // Control operations
1467 if (inst->isControl())
1468 exe_branches[thread_number]++;
1471 // Memory operations
1473 if (inst->isMemRef()) {
1474 exe_refs[thread_number]++;
1477 exe_loads[thread_number]++;
1481 template <class Impl>
1483 LWBackEnd<Impl>::updateComInstStats(DynInstPtr &inst)
1485 unsigned tid = inst->threadNumber;
1487 // keep an instruction count
1493 // Pick off the software prefetches
1496 if (inst->isDataPrefetch()) {
1497 stat_com_swp[tid]++;
1499 stat_com_inst[tid]++;
1502 stat_com_inst[tid]++;
1506 // Control Instructions
1508 if (inst->isControl())
1509 stat_com_branches[tid]++;
1512 // Memory references
1514 if (inst->isMemRef()) {
1515 stat_com_refs[tid]++;
1517 if (inst->isLoad()) {
1518 stat_com_loads[tid]++;
1522 if (inst->isMemBarrier()) {
1523 stat_com_membars[tid]++;
1527 template <class Impl>
1529 LWBackEnd<Impl>::dumpInsts()
1534 InstListIt inst_list_it = --(instList.end());
1536 cprintf("ExeList size: %i\n", exeList.size());
1538 cprintf("Inst list size: %i\n", instList.size());
1540 while (inst_list_it != instList.end())
1542 cprintf("Instruction:%i\n",
1544 if (!(*inst_list_it)->isSquashed()) {
1545 if (!(*inst_list_it)->isIssued()) {
1547 cprintf("Count:%i\n", valid_num);
1548 } else if ((*inst_list_it)->isMemRef() &&
1549 !(*inst_list_it)->memOpDone) {
1550 // Loads that have not been marked as executed still count
1551 // towards the total instructions.
1553 cprintf("Count:%i\n", valid_num);
1557 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1558 "Issued:%i\nSquashed:%i\n",
1559 (*inst_list_it)->readPC(),
1560 (*inst_list_it)->seqNum,
1561 (*inst_list_it)->threadNumber,
1562 (*inst_list_it)->isIssued(),
1563 (*inst_list_it)->isSquashed());
1565 if ((*inst_list_it)->isMemRef()) {
1566 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1575 cprintf("Waiting list size: %i\n", waitingList.size());
1577 inst_list_it = --(waitingList.end());
1579 while (inst_list_it != waitingList.end())
1581 cprintf("Instruction:%i\n",
1583 if (!(*inst_list_it)->isSquashed()) {
1584 if (!(*inst_list_it)->isIssued()) {
1586 cprintf("Count:%i\n", valid_num);
1587 } else if ((*inst_list_it)->isMemRef() &&
1588 !(*inst_list_it)->memOpDone) {
1589 // Loads that have not been marked as executed still count
1590 // towards the total instructions.
1592 cprintf("Count:%i\n", valid_num);
1596 cprintf("PC:%#x\n[sn:%lli]\n[tid:%i]\n"
1597 "Issued:%i\nSquashed:%i\n",
1598 (*inst_list_it)->readPC(),
1599 (*inst_list_it)->seqNum,
1600 (*inst_list_it)->threadNumber,
1601 (*inst_list_it)->isIssued(),
1602 (*inst_list_it)->isSquashed());
1604 if ((*inst_list_it)->isMemRef()) {
1605 cprintf("MemOpDone:%i\n", (*inst_list_it)->memOpDone);
1614 cprintf("waitingMemOps list size: %i\n", waitingMemOps.size());
1616 MemIt waiting_it = waitingMemOps.begin();
1618 while (waiting_it != waitingMemOps.end())
1620 cprintf("[sn:%lli] ", (*waiting_it));