src/cpu/ozone/lw_lsq_impl.hh

   1 /*
   2  * Copyright (c) 2004-2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "arch/isa_traits.hh"
  30 #include "base/str.hh"
  31 #include "cpu/ozone/lw_lsq.hh"
  32 #include "cpu/checker/cpu.hh"
  33
  34 template <class Impl>
  35 OzoneLWLSQ<Impl>::StoreCompletionEvent::StoreCompletionEvent(DynInstPtr &_inst,
  36                                                              BackEnd *_be,
  37                                                              Event *wb_event,
  38                                                              OzoneLWLSQ<Impl> *lsq_ptr)
  39     : Event(&mainEventQueue),
  40       inst(_inst),
  41       be(_be),
  42       wbEvent(wb_event),
  43       miss(false),
  44       lsqPtr(lsq_ptr)
  45 {
  46     this->setFlags(Event::AutoDelete);
  47 }
  48
  49 template <class Impl>
  50 void
  51 OzoneLWLSQ<Impl>::StoreCompletionEvent::process()
  52 {
  53     DPRINTF(OzoneLSQ, "Cache miss complete for store [sn:%lli]\n",
  54             inst->seqNum);
  55
  56     //lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum);
  57
  58 //    lsqPtr->cpu->wakeCPU();
  59     if (lsqPtr->isSwitchedOut()) {
  60         if (wbEvent)
  61             delete wbEvent;
  62
  63         return;
  64     }
  65
  66     if (wbEvent) {
  67         wbEvent->process();
  68         delete wbEvent;
  69     }
  70
  71     lsqPtr->completeStore(inst->sqIdx);
  72     if (miss)
  73         be->removeDcacheMiss(inst);
  74 }
  75
  76 template <class Impl>
  77 const char *
  78 OzoneLWLSQ<Impl>::StoreCompletionEvent::description()
  79 {
  80     return "LSQ store completion event";
  81 }
  82
  83 template <class Impl>
  84 OzoneLWLSQ<Impl>::OzoneLWLSQ()
  85     : loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false),
  86       loadBlockedHandled(false)
  87 {
  88 }
  89
  90 template<class Impl>
  91 void
  92 OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
  93                        unsigned maxSQEntries, unsigned id)
  94 {
  95     DPRINTF(OzoneLSQ, "Creating OzoneLWLSQ%i object.\n",id);
  96
  97     lsqID = id;
  98
  99     LQEntries = maxLQEntries;
 100     SQEntries = maxSQEntries;
 101
 102     for (int i = 0; i < LQEntries * 2; i++) {
 103         LQIndices.push(i);
 104         SQIndices.push(i);
 105     }
 106
 107     usedPorts = 0;
 108     cachePorts = params->cachePorts;
 109
 110     dcacheInterface = params->dcacheInterface;
 111
 112     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 113
 114     blockedLoadSeqNum = 0;
 115 }
 116
 117 template<class Impl>
 118 std::string
 119 OzoneLWLSQ<Impl>::name() const
 120 {
 121     return "lsqunit";
 122 }
 123
 124 template<class Impl>
 125 void
 126 OzoneLWLSQ<Impl>::clearLQ()
 127 {
 128     loadQueue.clear();
 129 }
 130
 131 template<class Impl>
 132 void
 133 OzoneLWLSQ<Impl>::clearSQ()
 134 {
 135     storeQueue.clear();
 136 }
 137 /*
 138 template<class Impl>
 139 void
 140 OzoneLWLSQ<Impl>::setPageTable(PageTable *pt_ptr)
 141 {
 142     DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
 143     pTable = pt_ptr;
 144 }
 145 */
 146 template<class Impl>
 147 void
 148 OzoneLWLSQ<Impl>::resizeLQ(unsigned size)
 149 {
 150     assert( size >= LQEntries);
 151
 152     if (size > LQEntries) {
 153         while (size > loadQueue.size()) {
 154             DynInstPtr dummy;
 155             loadQueue.push_back(dummy);
 156             LQEntries++;
 157         }
 158     } else {
 159         LQEntries = size;
 160     }
 161
 162 }
 163
 164 template<class Impl>
 165 void
 166 OzoneLWLSQ<Impl>::resizeSQ(unsigned size)
 167 {
 168     if (size > SQEntries) {
 169         while (size > storeQueue.size()) {
 170             SQEntry dummy;
 171             storeQueue.push_back(dummy);
 172             SQEntries++;
 173         }
 174     } else {
 175         SQEntries = size;
 176     }
 177 }
 178
 179 template <class Impl>
 180 void
 181 OzoneLWLSQ<Impl>::insert(DynInstPtr &inst)
 182 {
 183     // Make sure we really have a memory reference.
 184     assert(inst->isMemRef());
 185
 186     // Make sure it's one of the two classes of memory references.
 187     assert(inst->isLoad() || inst->isStore());
 188
 189     if (inst->isLoad()) {
 190         insertLoad(inst);
 191     } else {
 192         insertStore(inst);
 193     }
 194 }
 195
 196 template <class Impl>
 197 void
 198 OzoneLWLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
 199 {
 200     assert(loads < LQEntries * 2);
 201     assert(!LQIndices.empty());
 202     int load_index = LQIndices.front();
 203     LQIndices.pop();
 204
 205     DPRINTF(OzoneLSQ, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
 206             load_inst->readPC(), load_index, load_inst->seqNum);
 207
 208     load_inst->lqIdx = load_index;
 209
 210     loadQueue.push_front(load_inst);
 211     LQItHash[load_index] = loadQueue.begin();
 212
 213     ++loads;
 214 }
 215
 216 template <class Impl>
 217 void
 218 OzoneLWLSQ<Impl>::insertStore(DynInstPtr &store_inst)
 219 {
 220     // Make sure it is not full before inserting an instruction.
 221     assert(stores - storesToWB < SQEntries);
 222
 223     assert(!SQIndices.empty());
 224     int store_index = SQIndices.front();
 225     SQIndices.pop();
 226
 227     DPRINTF(OzoneLSQ, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
 228             store_inst->readPC(), store_index, store_inst->seqNum);
 229
 230     store_inst->sqIdx = store_index;
 231     SQEntry entry(store_inst);
 232     if (loadQueue.empty()) {
 233         entry.lqIt = loadQueue.end();
 234     } else {
 235         entry.lqIt = loadQueue.begin();
 236     }
 237     storeQueue.push_front(entry);
 238
 239     SQItHash[store_index] = storeQueue.begin();
 240
 241     ++stores;
 242 }
 243
 244 template <class Impl>
 245 typename Impl::DynInstPtr
 246 OzoneLWLSQ<Impl>::getMemDepViolator()
 247 {
 248     DynInstPtr temp = memDepViolator;
 249
 250     memDepViolator = NULL;
 251
 252     return temp;
 253 }
 254
 255 template <class Impl>
 256 unsigned
 257 OzoneLWLSQ<Impl>::numFreeEntries()
 258 {
 259     unsigned free_lq_entries = LQEntries - loads;
 260     unsigned free_sq_entries = SQEntries - stores;
 261
 262     // Both the LQ and SQ entries have an extra dummy entry to differentiate
 263     // empty/full conditions.  Subtract 1 from the free entries.
 264     if (free_lq_entries < free_sq_entries) {
 265         return free_lq_entries - 1;
 266     } else {
 267         return free_sq_entries - 1;
 268     }
 269 }
 270
 271 template <class Impl>
 272 int
 273 OzoneLWLSQ<Impl>::numLoadsReady()
 274 {
 275     int retval = 0;
 276     LQIt lq_it = loadQueue.begin();
 277     LQIt end_it = loadQueue.end();
 278
 279     while (lq_it != end_it) {
 280         if ((*lq_it)->readyToIssue()) {
 281             ++retval;
 282         }
 283     }
 284
 285     return retval;
 286 }
 287
 288 template <class Impl>
 289 Fault
 290 OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst)
 291 {
 292     // Execute a specific load.
 293     Fault load_fault = NoFault;
 294
 295     DPRINTF(OzoneLSQ, "Executing load PC %#x, [sn:%lli]\n",
 296             inst->readPC(),inst->seqNum);
 297
 298     // Make sure it's really in the list.
 299     // Normally it should always be in the list.  However,
 300     /* due to a syscall it may not be the list.
 301 #ifdef DEBUG
 302     int i = loadHead;
 303     while (1) {
 304         if (i == loadTail && !find(inst)) {
 305             assert(0 && "Load not in the queue!");
 306         } else if (loadQueue[i] == inst) {
 307             break;
 308         }
 309
 310         i = i + 1;
 311         if (i >= LQEntries) {
 312             i = 0;
 313         }
 314     }
 315 #endif // DEBUG*/
 316
 317     load_fault = inst->initiateAcc();
 318
 319     // Might want to make sure that I'm not overwriting a previously faulting
 320     // instruction that hasn't been checked yet.
 321     // Actually probably want the oldest faulting load
 322     if (load_fault != NoFault) {
 323         DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum);
 324         // Maybe just set it as can commit here, although that might cause
 325         // some other problems with sending traps to the ROB too quickly.
 326         be->instToCommit(inst);
 327 //        iewStage->activityThisCycle();
 328     }
 329
 330     return load_fault;
 331 }
 332
 333 template <class Impl>
 334 Fault
 335 OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
 336 {
 337     // Make sure that a store exists.
 338     assert(stores != 0);
 339
 340     int store_idx = store_inst->sqIdx;
 341     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 342     assert(sq_hash_it != SQItHash.end());
 343     DPRINTF(OzoneLSQ, "Executing store PC %#x [sn:%lli]\n",
 344             store_inst->readPC(), store_inst->seqNum);
 345
 346     SQIt sq_it = (*sq_hash_it).second;
 347
 348     Fault store_fault = store_inst->initiateAcc();
 349
 350     // Store size should now be available.  Use it to get proper offset for
 351     // addr comparisons.
 352     int size = (*sq_it).size;
 353
 354     if (size == 0) {
 355         DPRINTF(OzoneLSQ,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
 356                 store_inst->readPC(),store_inst->seqNum);
 357
 358         return store_fault;
 359     }
 360
 361     assert(store_fault == NoFault);
 362
 363     if (!storeFaultInst) {
 364         if (store_fault != NoFault) {
 365             panic("Fault in a store instruction!");
 366             storeFaultInst = store_inst;
 367         } else if (store_inst->isStoreConditional()) {
 368             // Store conditionals need to set themselves as able to
 369             // writeback if we haven't had a fault by here.
 370             (*sq_it).canWB = true;
 371
 372             ++storesToWB;
 373             DPRINTF(OzoneLSQ, "Nonspeculative store! storesToWB:%i\n",
 374                     storesToWB);
 375         }
 376     }
 377
 378     LQIt lq_it = --(loadQueue.end());
 379
 380     if (!memDepViolator) {
 381         while (lq_it != loadQueue.end()) {
 382             if ((*lq_it)->seqNum < store_inst->seqNum) {
 383                 lq_it--;
 384                 continue;
 385             }
 386             // Actually should only check loads that have actually executed
 387             // Might be safe because effAddr is set to InvalAddr when the
 388             // dyn inst is created.
 389
 390             // Must actually check all addrs in the proper size range
 391             // Which is more correct than needs to be.  What if for now we just
 392             // assume all loads are quad-word loads, and do the addr based
 393             // on that.
 394             // @todo: Fix this, magic number being used here
 395             if (((*lq_it)->effAddr >> 8) ==
 396                 (store_inst->effAddr >> 8)) {
 397                 // A load incorrectly passed this store.  Squash and refetch.
 398                 // For now return a fault to show that it was unsuccessful.
 399                 memDepViolator = (*lq_it);
 400
 401                 return TheISA::genMachineCheckFault();
 402             }
 403
 404             lq_it--;
 405         }
 406
 407         // If we've reached this point, there was no violation.
 408         memDepViolator = NULL;
 409     }
 410
 411     return store_fault;
 412 }
 413
 414 template <class Impl>
 415 void
 416 OzoneLWLSQ<Impl>::commitLoad()
 417 {
 418     assert(!loadQueue.empty());
 419
 420     DPRINTF(OzoneLSQ, "[sn:%lli] Committing head load instruction, PC %#x\n",
 421             loadQueue.back()->seqNum, loadQueue.back()->readPC());
 422
 423     LQIndices.push(loadQueue.back()->lqIdx);
 424     LQItHash.erase(loadQueue.back()->lqIdx);
 425
 426     loadQueue.pop_back();
 427
 428     --loads;
 429 }
 430
 431 template <class Impl>
 432 void
 433 OzoneLWLSQ<Impl>::commitLoads(InstSeqNum &youngest_inst)
 434 {
 435     assert(loads == 0 || !loadQueue.empty());
 436
 437     while (loads != 0 &&
 438            loadQueue.back()->seqNum <= youngest_inst) {
 439         commitLoad();
 440     }
 441 }
 442
 443 template <class Impl>
 444 void
 445 OzoneLWLSQ<Impl>::commitStores(InstSeqNum &youngest_inst)
 446 {
 447     assert(stores == 0 || !storeQueue.empty());
 448
 449     SQIt sq_it = --(storeQueue.end());
 450     while (!storeQueue.empty() && sq_it != storeQueue.end()) {
 451         assert((*sq_it).inst);
 452         if (!(*sq_it).canWB) {
 453             if ((*sq_it).inst->seqNum > youngest_inst) {
 454                 break;
 455             }
 456             ++storesToWB;
 457
 458             DPRINTF(OzoneLSQ, "Marking store as able to write back, PC "
 459                     "%#x [sn:%lli], storesToWB:%i\n",
 460                     (*sq_it).inst->readPC(),
 461                     (*sq_it).inst->seqNum,
 462                     storesToWB);
 463
 464             (*sq_it).canWB = true;
 465         }
 466
 467         sq_it--;
 468     }
 469 }
 470
 471 template <class Impl>
 472 void
 473 OzoneLWLSQ<Impl>::writebackStores()
 474 {
 475     SQIt sq_it = --(storeQueue.end());
 476     while (storesToWB > 0 &&
 477            sq_it != storeQueue.end() &&
 478            (*sq_it).inst &&
 479            (*sq_it).canWB &&
 480            usedPorts < cachePorts) {
 481
 482         DynInstPtr inst = (*sq_it).inst;
 483
 484         if ((*sq_it).size == 0 && !(*sq_it).completed) {
 485             sq_it--;
 486             completeStore(inst->sqIdx);
 487
 488             continue;
 489         }
 490
 491         if (inst->isDataPrefetch() || (*sq_it).committed) {
 492             sq_it--;
 493             continue;
 494         }
 495
 496         if (dcacheInterface && dcacheInterface->isBlocked()) {
 497             DPRINTF(OzoneLSQ, "Unable to write back any more stores, cache"
 498                     " is blocked!\n");
 499             break;
 500         }
 501
 502         ++usedPorts;
 503
 504         assert((*sq_it).req);
 505         assert(!(*sq_it).committed);
 506
 507         (*sq_it).committed = true;
 508
 509         MemReqPtr req = (*sq_it).req;
 510
 511         req->cmd = Write;
 512         req->completionEvent = NULL;
 513         req->time = curTick;
 514
 515         switch((*sq_it).size) {
 516           case 1:
 517             cpu->write(req, (uint8_t &)(*sq_it).data);
 518             break;
 519           case 2:
 520             cpu->write(req, (uint16_t &)(*sq_it).data);
 521             break;
 522           case 4:
 523             cpu->write(req, (uint32_t &)(*sq_it).data);
 524             break;
 525           case 8:
 526             cpu->write(req, (uint64_t &)(*sq_it).data);
 527             break;
 528           default:
 529             panic("Unexpected store size!\n");
 530         }
 531         if (!(req->flags & LOCKED)) {
 532             (*sq_it).inst->setCompleted();
 533             if (cpu->checker) {
 534                 cpu->checker->tick((*sq_it).inst);
 535             }
 536         }
 537
 538         DPRINTF(OzoneLSQ, "D-Cache: Writing back store idx:%i PC:%#x "
 539                 "to Addr:%#x, data:%#x [sn:%lli]\n",
 540                 inst->sqIdx,inst->readPC(),
 541                 req->paddr, *(req->data),
 542                 inst->seqNum);
 543
 544         if (dcacheInterface) {
 545             assert(!req->completionEvent);
 546             StoreCompletionEvent *store_event = new
 547                 StoreCompletionEvent(inst, be, NULL, this);
 548             req->completionEvent = store_event;
 549
 550             MemAccessResult result = dcacheInterface->access(req);
 551
 552             if (isStalled() &&
 553                 inst->seqNum == stallingStoreIsn) {
 554                 DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 555                         "load [sn:%lli]\n",
 556                         stallingStoreIsn, (*stallingLoad)->seqNum);
 557                 stalled = false;
 558                 stallingStoreIsn = 0;
 559                 be->replayMemInst((*stallingLoad));
 560             }
 561
 562             if (result != MA_HIT && dcacheInterface->doEvents()) {
 563                 store_event->miss = true;
 564                 typename BackEnd::LdWritebackEvent *wb = NULL;
 565                 if (req->flags & LOCKED) {
 566                     wb = new typename BackEnd::LdWritebackEvent(inst,
 567                                                             be);
 568                     store_event->wbEvent = wb;
 569                 }
 570
 571                 DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
 572
 573 //                DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
 574 //                        inst->seqNum);
 575
 576                 be->addDcacheMiss(inst);
 577
 578                 lastDcacheStall = curTick;
 579
 580                 _status = DcacheMissStall;
 581
 582                 // Increment stat here or something
 583
 584                 sq_it--;
 585             } else {
 586                 DPRINTF(OzoneLSQ,"D-Cache: Write Hit on idx:%i !\n",
 587                         inst->sqIdx);
 588
 589 //                DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 590 //                        inst->seqNum);
 591
 592                 if (req->flags & LOCKED) {
 593                     // Stx_C does not generate a system port
 594                     // transaction in the 21264, but that might be
 595                     // hard to accomplish in this model.
 596
 597                     typename BackEnd::LdWritebackEvent *wb =
 598                         new typename BackEnd::LdWritebackEvent(inst,
 599                                                                be);
 600                     store_event->wbEvent = wb;
 601                 }
 602                 sq_it--;
 603             }
 604         } else {
 605             panic("Must HAVE DCACHE!!!!!\n");
 606         }
 607     }
 608
 609     // Not sure this should set it to 0.
 610     usedPorts = 0;
 611
 612     assert(stores >= 0 && storesToWB >= 0);
 613 }
 614
 615 template <class Impl>
 616 void
 617 OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
 618 {
 619     DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
 620             "(Loads:%i Stores:%i)\n",squashed_num,loads,stores);
 621
 622
 623     LQIt lq_it = loadQueue.begin();
 624
 625     while (loads != 0 && (*lq_it)->seqNum > squashed_num) {
 626         assert(!loadQueue.empty());
 627         // Clear the smart pointer to make sure it is decremented.
 628         DPRINTF(OzoneLSQ,"Load Instruction PC %#x squashed, "
 629                 "[sn:%lli]\n",
 630                 (*lq_it)->readPC(),
 631                 (*lq_it)->seqNum);
 632
 633         if (isStalled() && lq_it == stallingLoad) {
 634             stalled = false;
 635             stallingStoreIsn = 0;
 636             stallingLoad = NULL;
 637         }
 638
 639         --loads;
 640
 641         // Inefficient!
 642         LQHashIt lq_hash_it = LQItHash.find((*lq_it)->lqIdx);
 643         assert(lq_hash_it != LQItHash.end());
 644         LQItHash.erase(lq_hash_it);
 645         LQIndices.push((*lq_it)->lqIdx);
 646         loadQueue.erase(lq_it++);
 647     }
 648
 649     if (isLoadBlocked) {
 650         if (squashed_num < blockedLoadSeqNum) {
 651             isLoadBlocked = false;
 652             loadBlockedHandled = false;
 653             blockedLoadSeqNum = 0;
 654         }
 655     }
 656
 657     SQIt sq_it = storeQueue.begin();
 658
 659     while (stores != 0 && (*sq_it).inst->seqNum > squashed_num) {
 660         assert(!storeQueue.empty());
 661
 662         if ((*sq_it).canWB) {
 663             break;
 664         }
 665
 666         // Clear the smart pointer to make sure it is decremented.
 667         DPRINTF(OzoneLSQ,"Store Instruction PC %#x idx:%i squashed [sn:%lli]\n",
 668                 (*sq_it).inst->readPC(), (*sq_it).inst->sqIdx,
 669                 (*sq_it).inst->seqNum);
 670
 671         // I don't think this can happen.  It should have been cleared by the
 672         // stalling load.
 673         if (isStalled() &&
 674             (*sq_it).inst->seqNum == stallingStoreIsn) {
 675             panic("Is stalled should have been cleared by stalling load!\n");
 676             stalled = false;
 677             stallingStoreIsn = 0;
 678         }
 679
 680         SQHashIt sq_hash_it = SQItHash.find((*sq_it).inst->sqIdx);
 681         assert(sq_hash_it != SQItHash.end());
 682         SQItHash.erase(sq_hash_it);
 683         SQIndices.push((*sq_it).inst->sqIdx);
 684         (*sq_it).inst = NULL;
 685         (*sq_it).canWB = 0;
 686
 687         if ((*sq_it).req) {
 688             assert(!(*sq_it).req->completionEvent);
 689         }
 690         (*sq_it).req = NULL;
 691         --stores;
 692         storeQueue.erase(sq_it++);
 693     }
 694 }
 695
 696 template <class Impl>
 697 void
 698 OzoneLWLSQ<Impl>::dumpInsts()
 699 {
 700     cprintf("Load store queue: Dumping instructions.\n");
 701     cprintf("Load queue size: %i\n", loads);
 702     cprintf("Load queue: ");
 703
 704     LQIt lq_it = --(loadQueue.end());
 705
 706     while (lq_it != loadQueue.end() && (*lq_it)) {
 707         cprintf("[sn:%lli] %#x ", (*lq_it)->seqNum,
 708                 (*lq_it)->readPC());
 709
 710         lq_it--;
 711     }
 712
 713     cprintf("\nStore queue size: %i\n", stores);
 714     cprintf("Store queue: ");
 715
 716     SQIt sq_it = --(storeQueue.end());
 717
 718     while (sq_it != storeQueue.end() && (*sq_it).inst) {
 719         cprintf("[sn:%lli]\nPC:%#x\nSize:%i\nCommitted:%i\nCompleted:%i\ncanWB:%i\n",
 720                 (*sq_it).inst->seqNum,
 721                 (*sq_it).inst->readPC(),
 722                 (*sq_it).size,
 723                 (*sq_it).committed,
 724                 (*sq_it).completed,
 725                 (*sq_it).canWB);
 726
 727         sq_it--;
 728     }
 729
 730     cprintf("\n");
 731 }
 732
 733 template <class Impl>
 734 void
 735 OzoneLWLSQ<Impl>::completeStore(int store_idx)
 736 {
 737     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 738     assert(sq_hash_it != SQItHash.end());
 739     SQIt sq_it = (*sq_hash_it).second;
 740
 741     assert((*sq_it).inst);
 742     (*sq_it).completed = true;
 743     DynInstPtr inst = (*sq_it).inst;
 744
 745     --storesToWB;
 746
 747     if (isStalled() &&
 748         inst->seqNum == stallingStoreIsn) {
 749         DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 750                 "load [sn:%lli]\n",
 751                 stallingStoreIsn, (*stallingLoad)->seqNum);
 752         stalled = false;
 753         stallingStoreIsn = 0;
 754         be->replayMemInst((*stallingLoad));
 755     }
 756
 757     DPRINTF(OzoneLSQ, "Completing store idx:%i [sn:%lli], storesToWB:%i\n",
 758             inst->sqIdx, inst->seqNum, storesToWB);
 759
 760     assert(!storeQueue.empty());
 761     SQItHash.erase(sq_hash_it);
 762     SQIndices.push(inst->sqIdx);
 763     storeQueue.erase(sq_it);
 764     --stores;
 765
 766     inst->setCompleted();
 767     if (cpu->checker) {
 768         cpu->checker->tick(inst);
 769     }
 770 }
 771
 772 template <class Impl>
 773 void
 774 OzoneLWLSQ<Impl>::switchOut()
 775 {
 776     assert(storesToWB == 0);
 777     switchedOut = true;
 778     SQIt sq_it = --(storeQueue.end());
 779     while (storesToWB > 0 &&
 780            sq_it != storeQueue.end() &&
 781            (*sq_it).inst &&
 782            (*sq_it).canWB) {
 783
 784         DynInstPtr inst = (*sq_it).inst;
 785
 786         if ((*sq_it).size == 0 && !(*sq_it).completed) {
 787             sq_it--;
 788             continue;
 789         }
 790
 791         // Store conditionals don't complete until *after* they have written
 792         // back.  If it's here and not yet sent to memory, then don't bother
 793         // as it's not part of committed state.
 794         if (inst->isDataPrefetch() || (*sq_it).committed) {
 795             sq_it--;
 796             continue;
 797         } else if ((*sq_it).req->flags & LOCKED) {
 798             sq_it--;
 799             assert(!(*sq_it).canWB ||
 800                    ((*sq_it).canWB && (*sq_it).req->flags & LOCKED));
 801             continue;
 802         }
 803
 804         assert((*sq_it).req);
 805         assert(!(*sq_it).committed);
 806
 807         MemReqPtr req = (*sq_it).req;
 808         (*sq_it).committed = true;
 809
 810         req->cmd = Write;
 811         req->completionEvent = NULL;
 812         req->time = curTick;
 813         assert(!req->data);
 814         req->data = new uint8_t[64];
 815         memcpy(req->data, (uint8_t *)&(*sq_it).data, req->size);
 816
 817         DPRINTF(OzoneLSQ, "Switching out : Writing back store idx:%i PC:%#x "
 818                 "to Addr:%#x, data:%#x directly to memory [sn:%lli]\n",
 819                 inst->sqIdx,inst->readPC(),
 820                 req->paddr, *(req->data),
 821                 inst->seqNum);
 822
 823         switch((*sq_it).size) {
 824           case 1:
 825             cpu->write(req, (uint8_t &)(*sq_it).data);
 826             break;
 827           case 2:
 828             cpu->write(req, (uint16_t &)(*sq_it).data);
 829             break;
 830           case 4:
 831             cpu->write(req, (uint32_t &)(*sq_it).data);
 832             break;
 833           case 8:
 834             cpu->write(req, (uint64_t &)(*sq_it).data);
 835             break;
 836           default:
 837             panic("Unexpected store size!\n");
 838         }
 839     }
 840
 841     // Clear the queue to free up resources
 842     storeQueue.clear();
 843     loadQueue.clear();
 844     loads = stores = storesToWB = 0;
 845 }
 846
 847 template <class Impl>
 848 void
 849 OzoneLWLSQ<Impl>::takeOverFrom(ThreadContext *old_tc)
 850 {
 851     // Clear out any old state. May be redundant if this is the first time
 852     // the CPU is being used.
 853     stalled = false;
 854     isLoadBlocked = false;
 855     loadBlockedHandled = false;
 856     switchedOut = false;
 857
 858     // Could do simple checks here to see if indices are on twice
 859     while (!LQIndices.empty())
 860         LQIndices.pop();
 861     while (!SQIndices.empty())
 862         SQIndices.pop();
 863
 864     for (int i = 0; i < LQEntries * 2; i++) {
 865         LQIndices.push(i);
 866         SQIndices.push(i);
 867     }
 868
 869     usedPorts = 0;
 870
 871     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 872
 873     blockedLoadSeqNum = 0;
 874 }