src/cpu/ozone/lw_lsq_impl.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "config/use_checker.hh"
  32
  33 #include "arch/faults.hh"
  34 #include "base/str.hh"
  35 #include "cpu/ozone/lw_lsq.hh"
  36 #include "cpu/checker/cpu.hh"
  37
  38 template<class Impl>
  39 OzoneLWLSQ<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
  40                                                  OzoneLWLSQ *lsq_ptr)
  41     : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
  42 {
  43     this->setFlags(Event::AutoDelete);
  44 }
  45
  46 template<class Impl>
  47 void
  48 OzoneLWLSQ<Impl>::WritebackEvent::process()
  49 {
  50     if (!lsqPtr->isSwitchedOut()) {
  51         lsqPtr->writeback(inst, pkt);
  52     }
  53     delete pkt;
  54 }
  55
  56 template<class Impl>
  57 const char *
  58 OzoneLWLSQ<Impl>::WritebackEvent::description()
  59 {
  60     return "Store writeback event";
  61 }
  62
  63 template <class Impl>
  64 Tick
  65 OzoneLWLSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
  66 {
  67     panic("O3CPU model does not work with atomic mode!");
  68     return curTick;
  69 }
  70
  71 template <class Impl>
  72 void
  73 OzoneLWLSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
  74 {
  75     panic("O3CPU doesn't expect recvFunctional callback!");
  76 }
  77
  78 template <class Impl>
  79 void
  80 OzoneLWLSQ<Impl>::DcachePort::recvStatusChange(Status status)
  81 {
  82     if (status == RangeChange)
  83         return;
  84
  85     panic("O3CPU doesn't expect recvStatusChange callback!");
  86 }
  87
  88 template <class Impl>
  89 bool
  90 OzoneLWLSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
  91 {
  92     lsq->completeDataAccess(pkt);
  93     return true;
  94 }
  95
  96 template <class Impl>
  97 void
  98 OzoneLWLSQ<Impl>::DcachePort::recvRetry()
  99 {
 100     lsq->recvRetry();
 101 }
 102
 103 template<class Impl>
 104 void
 105 OzoneLWLSQ<Impl>::completeDataAccess(PacketPtr pkt)
 106 {
 107     LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
 108     DynInstPtr inst = state->inst;
 109     DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
 110     DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
 111
 112     //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
 113
 114     if (isSwitchedOut() || inst->isSquashed()) {
 115         delete state;
 116         delete pkt;
 117         return;
 118     } else {
 119         if (!state->noWB) {
 120             writeback(inst, pkt);
 121         }
 122
 123         if (inst->isStore()) {
 124             completeStore(state->idx);
 125         }
 126     }
 127
 128     delete state;
 129     delete pkt;
 130 }
 131
 132 template <class Impl>
 133 OzoneLWLSQ<Impl>::OzoneLWLSQ()
 134     : switchedOut(false), dcachePort(this), loads(0), stores(0),
 135       storesToWB(0), storesInFlight(0), stalled(false), isStoreBlocked(false),
 136       isLoadBlocked(false), loadBlockedHandled(false)
 137 {
 138 }
 139
 140 template<class Impl>
 141 void
 142 OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
 143                        unsigned maxSQEntries, unsigned id)
 144 {
 145     DPRINTF(OzoneLSQ, "Creating OzoneLWLSQ%i object.\n",id);
 146
 147     lsqID = id;
 148
 149     LQEntries = maxLQEntries;
 150     SQEntries = maxSQEntries;
 151
 152     for (int i = 0; i < LQEntries * 2; i++) {
 153         LQIndices.push(i);
 154         SQIndices.push(i);
 155     }
 156
 157     mem = params->mem;
 158
 159     usedPorts = 0;
 160     cachePorts = params->cachePorts;
 161
 162     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 163
 164     blockedLoadSeqNum = 0;
 165 }
 166
 167 template<class Impl>
 168 std::string
 169 OzoneLWLSQ<Impl>::name() const
 170 {
 171     return "lsqunit";
 172 }
 173
 174 template<class Impl>
 175 void
 176 OzoneLWLSQ<Impl>::regStats()
 177 {
 178     lsqMemOrderViolation
 179         .name(name() + ".memOrderViolation")
 180         .desc("Number of memory ordering violations");
 181 OzoneLWLSQ<Impl>::setCPU(OzoneCPU *cpu_ptr)
 182 {
 183     cpu = cpu_ptr;
 184     dcachePort.setName(this->name() + "-dport");
 185
 186 #if USE_CHECKER
 187     if (cpu->checker) {
 188         cpu->checker->setDcachePort(&dcachePort);
 189     }
 190 #endif
 191 }
 192
 193 template<class Impl>
 194 void
 195 OzoneLWLSQ<Impl>::clearLQ()
 196 {
 197     loadQueue.clear();
 198 }
 199
 200 template<class Impl>
 201 void
 202 OzoneLWLSQ<Impl>::clearSQ()
 203 {
 204     storeQueue.clear();
 205 }
 206 /*
 207 template<class Impl>
 208 void
 209 OzoneLWLSQ<Impl>::setPageTable(PageTable *pt_ptr)
 210 {
 211     DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
 212     pTable = pt_ptr;
 213 }
 214 */
 215 template<class Impl>
 216 void
 217 OzoneLWLSQ<Impl>::resizeLQ(unsigned size)
 218 {
 219     assert( size >= LQEntries);
 220
 221     if (size > LQEntries) {
 222         while (size > loadQueue.size()) {
 223             DynInstPtr dummy;
 224             loadQueue.push_back(dummy);
 225             LQEntries++;
 226         }
 227     } else {
 228         LQEntries = size;
 229     }
 230
 231 }
 232
 233 template<class Impl>
 234 void
 235 OzoneLWLSQ<Impl>::resizeSQ(unsigned size)
 236 {
 237     if (size > SQEntries) {
 238         while (size > storeQueue.size()) {
 239             SQEntry dummy;
 240             storeQueue.push_back(dummy);
 241             SQEntries++;
 242         }
 243     } else {
 244         SQEntries = size;
 245     }
 246 }
 247
 248 template <class Impl>
 249 void
 250 OzoneLWLSQ<Impl>::insert(DynInstPtr &inst)
 251 {
 252     // Make sure we really have a memory reference.
 253     assert(inst->isMemRef());
 254
 255     // Make sure it's one of the two classes of memory references.
 256     assert(inst->isLoad() || inst->isStore());
 257
 258     if (inst->isLoad()) {
 259         insertLoad(inst);
 260     } else {
 261         insertStore(inst);
 262     }
 263 }
 264
 265 template <class Impl>
 266 void
 267 OzoneLWLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
 268 {
 269     assert(loads < LQEntries * 2);
 270     assert(!LQIndices.empty());
 271     int load_index = LQIndices.front();
 272     LQIndices.pop();
 273
 274     DPRINTF(OzoneLSQ, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
 275             load_inst->readPC(), load_index, load_inst->seqNum);
 276
 277     load_inst->lqIdx = load_index;
 278
 279     loadQueue.push_front(load_inst);
 280     LQItHash[load_index] = loadQueue.begin();
 281
 282     ++loads;
 283 }
 284
 285 template <class Impl>
 286 void
 287 OzoneLWLSQ<Impl>::insertStore(DynInstPtr &store_inst)
 288 {
 289     // Make sure it is not full before inserting an instruction.
 290     assert(stores - storesToWB < SQEntries);
 291
 292     assert(!SQIndices.empty());
 293     int store_index = SQIndices.front();
 294     SQIndices.pop();
 295
 296     DPRINTF(OzoneLSQ, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
 297             store_inst->readPC(), store_index, store_inst->seqNum);
 298
 299     store_inst->sqIdx = store_index;
 300     SQEntry entry(store_inst);
 301     if (loadQueue.empty()) {
 302         entry.lqIt = loadQueue.end();
 303     } else {
 304         entry.lqIt = loadQueue.begin();
 305     }
 306     storeQueue.push_front(entry);
 307
 308     SQItHash[store_index] = storeQueue.begin();
 309
 310     ++stores;
 311 }
 312
 313 template <class Impl>
 314 typename Impl::DynInstPtr
 315 OzoneLWLSQ<Impl>::getMemDepViolator()
 316 {
 317     DynInstPtr temp = memDepViolator;
 318
 319     memDepViolator = NULL;
 320
 321     return temp;
 322 }
 323
 324 template <class Impl>
 325 unsigned
 326 OzoneLWLSQ<Impl>::numFreeEntries()
 327 {
 328     unsigned free_lq_entries = LQEntries - loads;
 329     unsigned free_sq_entries = SQEntries - (stores + storesInFlight);
 330
 331     // Both the LQ and SQ entries have an extra dummy entry to differentiate
 332     // empty/full conditions.  Subtract 1 from the free entries.
 333     if (free_lq_entries < free_sq_entries) {
 334         return free_lq_entries - 1;
 335     } else {
 336         return free_sq_entries - 1;
 337     }
 338 }
 339
 340 template <class Impl>
 341 int
 342 OzoneLWLSQ<Impl>::numLoadsReady()
 343 {
 344     int retval = 0;
 345     LQIt lq_it = loadQueue.begin();
 346     LQIt end_it = loadQueue.end();
 347
 348     while (lq_it != end_it) {
 349         if ((*lq_it)->readyToIssue()) {
 350             ++retval;
 351         }
 352     }
 353
 354     return retval;
 355 }
 356
 357 template <class Impl>
 358 Fault
 359 OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst)
 360 {
 361     // Execute a specific load.
 362     Fault load_fault = NoFault;
 363
 364     DPRINTF(OzoneLSQ, "Executing load PC %#x, [sn:%lli]\n",
 365             inst->readPC(),inst->seqNum);
 366
 367     // Make sure it's really in the list.
 368     // Normally it should always be in the list.  However,
 369     /* due to a syscall it may not be the list.
 370 #ifdef DEBUG
 371     int i = loadHead;
 372     while (1) {
 373         if (i == loadTail && !find(inst)) {
 374             assert(0 && "Load not in the queue!");
 375         } else if (loadQueue[i] == inst) {
 376             break;
 377         }
 378
 379         i = i + 1;
 380         if (i >= LQEntries) {
 381             i = 0;
 382         }
 383     }
 384 #endif // DEBUG*/
 385
 386     load_fault = inst->initiateAcc();
 387
 388     // Might want to make sure that I'm not overwriting a previously faulting
 389     // instruction that hasn't been checked yet.
 390     // Actually probably want the oldest faulting load
 391     if (load_fault != NoFault) {
 392         DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum);
 393         if (!(inst->req->flags & UNCACHEABLE && !inst->isAtCommit())) {
 394             inst->setExecuted();
 395         }
 396         // Maybe just set it as can commit here, although that might cause
 397         // some other problems with sending traps to the ROB too quickly.
 398         be->instToCommit(inst);
 399 //        iewStage->activityThisCycle();
 400     }
 401
 402     return load_fault;
 403 }
 404
 405 template <class Impl>
 406 Fault
 407 OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
 408 {
 409     // Make sure that a store exists.
 410     assert(stores != 0);
 411
 412     int store_idx = store_inst->sqIdx;
 413     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 414     assert(sq_hash_it != SQItHash.end());
 415     DPRINTF(OzoneLSQ, "Executing store PC %#x [sn:%lli]\n",
 416             store_inst->readPC(), store_inst->seqNum);
 417
 418     SQIt sq_it = (*sq_hash_it).second;
 419
 420     Fault store_fault = store_inst->initiateAcc();
 421
 422     // Store size should now be available.  Use it to get proper offset for
 423     // addr comparisons.
 424     int size = (*sq_it).size;
 425
 426     if (size == 0) {
 427         DPRINTF(OzoneLSQ,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
 428                 store_inst->readPC(),store_inst->seqNum);
 429
 430         return store_fault;
 431     }
 432
 433     assert(store_fault == NoFault);
 434
 435     if (!storeFaultInst) {
 436         if (store_fault != NoFault) {
 437             panic("Fault in a store instruction!");
 438             storeFaultInst = store_inst;
 439         } else if (store_inst->isStoreConditional()) {
 440             // Store conditionals need to set themselves as able to
 441             // writeback if we haven't had a fault by here.
 442             (*sq_it).canWB = true;
 443
 444             ++storesToWB;
 445             DPRINTF(OzoneLSQ, "Nonspeculative store! storesToWB:%i\n",
 446                     storesToWB);
 447         }
 448     }
 449
 450     LQIt lq_it = --(loadQueue.end());
 451
 452     if (!memDepViolator) {
 453         while (lq_it != loadQueue.end()) {
 454             if ((*lq_it)->seqNum < store_inst->seqNum) {
 455                 lq_it--;
 456                 continue;
 457             }
 458             // Actually should only check loads that have actually executed
 459             // Might be safe because effAddr is set to InvalAddr when the
 460             // dyn inst is created.
 461
 462             // Must actually check all addrs in the proper size range
 463             // Which is more correct than needs to be.  What if for now we just
 464             // assume all loads are quad-word loads, and do the addr based
 465             // on that.
 466             // @todo: Fix this, magic number being used here
 467             if (((*lq_it)->effAddr >> 8) ==
 468                 (store_inst->effAddr >> 8)) {
 469                 // A load incorrectly passed this store.  Squash and refetch.
 470                 // For now return a fault to show that it was unsuccessful.
 471                 memDepViolator = (*lq_it);
 472                 ++lsqMemOrderViolation;
 473
 474                 return TheISA::genMachineCheckFault();
 475             }
 476
 477             lq_it--;
 478         }
 479
 480         // If we've reached this point, there was no violation.
 481         memDepViolator = NULL;
 482     }
 483
 484     return store_fault;
 485 }
 486
 487 template <class Impl>
 488 void
 489 OzoneLWLSQ<Impl>::commitLoad()
 490 {
 491     assert(!loadQueue.empty());
 492
 493     DPRINTF(OzoneLSQ, "[sn:%lli] Committing head load instruction, PC %#x\n",
 494             loadQueue.back()->seqNum, loadQueue.back()->readPC());
 495
 496     LQIndices.push(loadQueue.back()->lqIdx);
 497     LQItHash.erase(loadQueue.back()->lqIdx);
 498
 499     loadQueue.pop_back();
 500
 501     --loads;
 502 }
 503
 504 template <class Impl>
 505 void
 506 OzoneLWLSQ<Impl>::commitLoads(InstSeqNum &youngest_inst)
 507 {
 508     assert(loads == 0 || !loadQueue.empty());
 509
 510     while (loads != 0 &&
 511            loadQueue.back()->seqNum <= youngest_inst) {
 512         commitLoad();
 513     }
 514 }
 515
 516 template <class Impl>
 517 void
 518 OzoneLWLSQ<Impl>::commitStores(InstSeqNum &youngest_inst)
 519 {
 520     assert(stores == 0 || !storeQueue.empty());
 521
 522     SQIt sq_it = --(storeQueue.end());
 523     while (!storeQueue.empty() && sq_it != storeQueue.end()) {
 524         assert((*sq_it).inst);
 525         if (!(*sq_it).canWB) {
 526             if ((*sq_it).inst->seqNum > youngest_inst) {
 527                 break;
 528             }
 529             ++storesToWB;
 530
 531             DPRINTF(OzoneLSQ, "Marking store as able to write back, PC "
 532                     "%#x [sn:%lli], storesToWB:%i\n",
 533                     (*sq_it).inst->readPC(),
 534                     (*sq_it).inst->seqNum,
 535                     storesToWB);
 536
 537             (*sq_it).canWB = true;
 538         }
 539
 540         sq_it--;
 541     }
 542 }
 543
 544 template <class Impl>
 545 void
 546 OzoneLWLSQ<Impl>::writebackStores()
 547 {
 548     SQIt sq_it = --(storeQueue.end());
 549     while (storesToWB > 0 &&
 550            sq_it != storeQueue.end() &&
 551            (*sq_it).inst &&
 552            (*sq_it).canWB &&
 553            usedPorts < cachePorts) {
 554
 555         if (isStoreBlocked) {
 556             DPRINTF(OzoneLSQ, "Unable to write back any more stores, cache"
 557                     " is blocked!\n");
 558             break;
 559         }
 560
 561         DynInstPtr inst = (*sq_it).inst;
 562
 563         if ((*sq_it).size == 0 && !(*sq_it).completed) {
 564             sq_it--;
 565             removeStore(inst->sqIdx);
 566             completeStore(inst);
 567             continue;
 568         }
 569
 570         if (inst->isDataPrefetch() || (*sq_it).committed) {
 571             sq_it--;
 572             continue;
 573         }
 574
 575         ++usedPorts;
 576
 577         assert((*sq_it).req);
 578         assert(!(*sq_it).committed);
 579
 580         Request *req = (*sq_it).req;
 581         (*sq_it).committed = true;
 582
 583         assert(!inst->memData);
 584         inst->memData = new uint8_t[64];
 585         memcpy(inst->memData, (uint8_t *)&(*sq_it).data,
 586                req->getSize());
 587
 588         PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
 589         data_pkt->dataStatic(inst->memData);
 590
 591         LSQSenderState *state = new LSQSenderState;
 592         state->isLoad = false;
 593         state->idx = inst->sqIdx;
 594         state->inst = inst;
 595         data_pkt->senderState = state;
 596
 597         DPRINTF(OzoneLSQ, "D-Cache: Writing back store PC:%#x "
 598                 "to Addr:%#x, data:%#x [sn:%lli]\n",
 599                 (*sq_it).inst->readPC(),
 600                 req->getPaddr(), *(inst->memData),
 601                 inst->seqNum);
 602
 603         // @todo: Remove this SC hack once the memory system handles it.
 604         if (req->getFlags() & LOCKED) {
 605             if (req->getFlags() & UNCACHEABLE) {
 606                 req->setScResult(2);
 607             } else {
 608                 if (cpu->lockFlag) {
 609                     req->setScResult(1);
 610                 } else {
 611                     req->setScResult(0);
 612                     // Hack: Instantly complete this store.
 613                     completeDataAccess(data_pkt);
 614                     --sq_it;
 615                     continue;
 616                 }
 617             }
 618         } else {
 619             // Non-store conditionals do not need a writeback.
 620             state->noWB = true;
 621         }
 622
 623         if (!dcachePort.sendTiming(data_pkt)) {
 624             // Need to handle becoming blocked on a store.
 625             isStoreBlocked = true;
 626             assert(retryPkt == NULL);
 627             retryPkt = data_pkt;
 628         } else {
 629             storePostSend(data_pkt, inst);
 630             --sq_it;
 631         }
 632 /*
 633         DPRINTF(OzoneLSQ, "D-Cache: Writing back store idx:%i PC:%#x "
 634                 "to Addr:%#x, data:%#x [sn:%lli]\n",
 635                 inst->sqIdx,inst->readPC(),
 636                 req->paddr, *(req->data),
 637                 inst->seqNum);
 638         DPRINTF(OzoneLSQ, "StoresInFlight: %i\n",
 639                 storesInFlight + 1);
 640
 641         if (dcacheInterface) {
 642             assert(!req->completionEvent);
 643             StoreCompletionEvent *store_event = new
 644                 StoreCompletionEvent(inst, be, NULL, this);
 645             req->completionEvent = store_event;
 646
 647             MemAccessResult result = dcacheInterface->access(req);
 648
 649             if (isStalled() &&
 650                 inst->seqNum == stallingStoreIsn) {
 651                 DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 652                         "load [sn:%lli]\n",
 653                         stallingStoreIsn, (*stallingLoad)->seqNum);
 654                 stalled = false;
 655                 stallingStoreIsn = 0;
 656                 be->replayMemInst((*stallingLoad));
 657             }
 658
 659             if (result != MA_HIT && dcacheInterface->doEvents()) {
 660                 store_event->miss = true;
 661                 typename BackEnd::LdWritebackEvent *wb = NULL;
 662                 if (req->flags & LOCKED) {
 663                     wb = new typename BackEnd::LdWritebackEvent(inst,
 664                                                             be);
 665                     store_event->wbEvent = wb;
 666                 }
 667
 668                 DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
 669
 670 //                DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
 671 //                        inst->seqNum);
 672
 673                 be->addDcacheMiss(inst);
 674
 675                 lastDcacheStall = curTick;
 676
 677                 _status = DcacheMissStall;
 678
 679                 // Increment stat here or something
 680
 681                 sq_it--;
 682             } else {
 683                 DPRINTF(OzoneLSQ,"D-Cache: Write Hit on idx:%i !\n",
 684                         inst->sqIdx);
 685
 686 //                DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 687 //                        inst->seqNum);
 688
 689                 if (req->flags & LOCKED) {
 690                     // Stx_C does not generate a system port
 691                     // transaction in the 21264, but that might be
 692                     // hard to accomplish in this model.
 693
 694                     typename BackEnd::LdWritebackEvent *wb =
 695                         new typename BackEnd::LdWritebackEvent(inst,
 696                                                                be);
 697                     store_event->wbEvent = wb;
 698                 }
 699                 sq_it--;
 700             }
 701             ++storesInFlight;
 702 //            removeStore(inst->sqIdx);
 703         } else {
 704             panic("Must HAVE DCACHE!!!!!\n");
 705         }
 706 */
 707     }
 708
 709     // Not sure this should set it to 0.
 710     usedPorts = 0;
 711
 712     assert(stores >= 0 && storesToWB >= 0);
 713 }
 714
 715 template <class Impl>
 716 void
 717 OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
 718 {
 719     DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
 720             "(Loads:%i Stores:%i)\n",squashed_num,loads,stores+storesInFlight);
 721
 722
 723     LQIt lq_it = loadQueue.begin();
 724
 725     while (loads != 0 && (*lq_it)->seqNum > squashed_num) {
 726         assert(!loadQueue.empty());
 727         // Clear the smart pointer to make sure it is decremented.
 728         DPRINTF(OzoneLSQ,"Load Instruction PC %#x squashed, "
 729                 "[sn:%lli]\n",
 730                 (*lq_it)->readPC(),
 731                 (*lq_it)->seqNum);
 732
 733         if (isStalled() && lq_it == stallingLoad) {
 734             stalled = false;
 735             stallingStoreIsn = 0;
 736             stallingLoad = NULL;
 737         }
 738
 739         --loads;
 740
 741         // Inefficient!
 742         LQHashIt lq_hash_it = LQItHash.find((*lq_it)->lqIdx);
 743         assert(lq_hash_it != LQItHash.end());
 744         LQItHash.erase(lq_hash_it);
 745         LQIndices.push((*lq_it)->lqIdx);
 746         loadQueue.erase(lq_it++);
 747     }
 748
 749     if (isLoadBlocked) {
 750         if (squashed_num < blockedLoadSeqNum) {
 751             isLoadBlocked = false;
 752             loadBlockedHandled = false;
 753             blockedLoadSeqNum = 0;
 754         }
 755     }
 756
 757     SQIt sq_it = storeQueue.begin();
 758
 759     while (stores != 0 && (*sq_it).inst->seqNum > squashed_num) {
 760         assert(!storeQueue.empty());
 761
 762         if ((*sq_it).canWB) {
 763             break;
 764         }
 765
 766         // Clear the smart pointer to make sure it is decremented.
 767         DPRINTF(OzoneLSQ,"Store Instruction PC %#x idx:%i squashed [sn:%lli]\n",
 768                 (*sq_it).inst->readPC(), (*sq_it).inst->sqIdx,
 769                 (*sq_it).inst->seqNum);
 770
 771         // I don't think this can happen.  It should have been cleared by the
 772         // stalling load.
 773         if (isStalled() &&
 774             (*sq_it).inst->seqNum == stallingStoreIsn) {
 775             panic("Is stalled should have been cleared by stalling load!\n");
 776             stalled = false;
 777             stallingStoreIsn = 0;
 778         }
 779
 780         SQHashIt sq_hash_it = SQItHash.find((*sq_it).inst->sqIdx);
 781         assert(sq_hash_it != SQItHash.end());
 782         SQItHash.erase(sq_hash_it);
 783         SQIndices.push((*sq_it).inst->sqIdx);
 784         (*sq_it).inst = NULL;
 785         (*sq_it).canWB = 0;
 786         (*sq_it).req = NULL;
 787         --stores;
 788         storeQueue.erase(sq_it++);
 789     }
 790 }
 791
 792 template <class Impl>
 793 void
 794 OzoneLWLSQ<Impl>::dumpInsts()
 795 {
 796     cprintf("Load store queue: Dumping instructions.\n");
 797     cprintf("Load queue size: %i\n", loads);
 798     cprintf("Load queue: ");
 799
 800     LQIt lq_it = --(loadQueue.end());
 801
 802     while (lq_it != loadQueue.end() && (*lq_it)) {
 803         cprintf("[sn:%lli] %#x ", (*lq_it)->seqNum,
 804                 (*lq_it)->readPC());
 805
 806         lq_it--;
 807     }
 808
 809     cprintf("\nStore queue size: %i\n", stores);
 810     cprintf("Store queue: ");
 811
 812     SQIt sq_it = --(storeQueue.end());
 813
 814     while (sq_it != storeQueue.end() && (*sq_it).inst) {
 815         cprintf("[sn:%lli]\nPC:%#x\nSize:%i\nCommitted:%i\nCompleted:%i\ncanWB:%i\n",
 816                 (*sq_it).inst->seqNum,
 817                 (*sq_it).inst->readPC(),
 818                 (*sq_it).size,
 819                 (*sq_it).committed,
 820                 (*sq_it).completed,
 821                 (*sq_it).canWB);
 822
 823         sq_it--;
 824     }
 825
 826     cprintf("\n");
 827 }
 828
 829 template <class Impl>
 830 void
 831 OzoneLWLSQ<Impl>::storePostSend(Packet *pkt, DynInstPtr &inst)
 832 {
 833     if (isStalled() &&
 834         inst->seqNum == stallingStoreIsn) {
 835         DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 836                 "load [sn:%lli]\n",
 837                 stallingStoreIsn, (*stallingLoad)->seqNum);
 838         stalled = false;
 839         stallingStoreIsn = 0;
 840         be->replayMemInst((*stallingLoad));
 841     }
 842
 843     if (!inst->isStoreConditional()) {
 844         // The store is basically completed at this time. This
 845         // only works so long as the checker doesn't try to
 846         // verify the value in memory for stores.
 847         inst->setCompleted();
 848 #if USE_CHECKER
 849         if (cpu->checker) {
 850             cpu->checker->verify(inst);
 851         }
 852 #endif
 853     }
 854
 855     if (pkt->result != Packet::Success) {
 856         DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
 857
 858         DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
 859                 inst->seqNum);
 860
 861         //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
 862
 863         //DPRINTF(OzoneLWLSQ, "Added MSHR. count = %i\n",mshrSeqNums.size());
 864
 865         // @todo: Increment stat here.
 866     } else {
 867         DPRINTF(OzoneLSQ,"D-Cache: Write Hit!\n");
 868
 869         DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 870                 inst->seqNum);
 871     }
 872 }
 873
 874 template <class Impl>
 875 void
 876 OzoneLWLSQ<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
 877 {
 878     // Squashed instructions do not need to complete their access.
 879     if (inst->isSquashed()) {
 880         assert(!inst->isStore());
 881         return;
 882     }
 883
 884     if (!inst->isExecuted()) {
 885         inst->setExecuted();
 886
 887         // Complete access to copy data to proper place.
 888         inst->completeAcc(pkt);
 889     }
 890
 891     // Need to insert instruction into queue to commit
 892     be->instToCommit(inst);
 893 }
 894
 895 template <class Impl>
 896 void
 897 OzoneLWLSQ<Impl>::removeStore(int store_idx)
 898 {
 899     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 900     assert(sq_hash_it != SQItHash.end());
 901     SQIt sq_it = (*sq_hash_it).second;
 902
 903     assert((*sq_it).inst);
 904     (*sq_it).completed = true;
 905     DynInstPtr inst = (*sq_it).inst;
 906
 907     if (isStalled() &&
 908         inst->seqNum == stallingStoreIsn) {
 909         DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 910                 "load [sn:%lli]\n",
 911                 stallingStoreIsn, (*stallingLoad)->seqNum);
 912         stalled = false;
 913         stallingStoreIsn = 0;
 914         be->replayMemInst((*stallingLoad));
 915     }
 916
 917     DPRINTF(OzoneLSQ, "Completing store idx:%i [sn:%lli], storesToWB:%i\n",
 918             inst->sqIdx, inst->seqNum, storesToWB);
 919
 920     assert(!storeQueue.empty());
 921     SQItHash.erase(sq_hash_it);
 922     SQIndices.push(inst->sqIdx);
 923     storeQueue.erase(sq_it);
 924 }
 925
 926 template <class Impl>
 927 void
 928 OzoneLWLSQ<Impl>::completeStore(DynInstPtr &inst)
 929 {
 930     --storesToWB;
 931     --stores;
 932
 933     inst->setCompleted();
 934 #if USE_CHECKER
 935     if (cpu->checker) {
 936         cpu->checker->verify(inst);
 937     }
 938 #endif
 939 }
 940
 941 template <class Impl>
 942 void
 943 OzoneLWLSQ<Impl>::recvRetry()
 944 {
 945     panic("Unimplemented!");
 946 }
 947
 948 template <class Impl>
 949 void
 950 OzoneLWLSQ<Impl>::switchOut()
 951 {
 952     assert(storesToWB == 0);
 953     switchedOut = true;
 954
 955     // Clear the queue to free up resources
 956     assert(stores == 0);
 957     assert(storeQueue.empty());
 958     assert(loads == 0);
 959     assert(loadQueue.empty());
 960     assert(storesInFlight == 0);
 961     storeQueue.clear();
 962     loadQueue.clear();
 963     loads = stores = storesToWB = storesInFlight = 0;
 964 }
 965
 966 template <class Impl>
 967 void
 968 OzoneLWLSQ<Impl>::takeOverFrom(ThreadContext *old_tc)
 969 {
 970     // Clear out any old state. May be redundant if this is the first time
 971     // the CPU is being used.
 972     stalled = false;
 973     isLoadBlocked = false;
 974     loadBlockedHandled = false;
 975     switchedOut = false;
 976
 977     // Could do simple checks here to see if indices are on twice
 978     while (!LQIndices.empty())
 979         LQIndices.pop();
 980     while (!SQIndices.empty())
 981         SQIndices.pop();
 982
 983     for (int i = 0; i < LQEntries * 2; i++) {
 984         LQIndices.push(i);
 985         SQIndices.push(i);
 986     }
 987
 988     usedPorts = 0;
 989
 990     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 991
 992     blockedLoadSeqNum = 0;
 993 }