src/cpu/ozone/lw_lsq_impl.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "base/str.hh"
  32 #include "config/the_isa.hh"
  33 #include "cpu/checker/cpu.hh"
  34 #include "cpu/ozone/lw_lsq.hh"
  35 #include "sim/fault_fwd.hh"
  36
  37 template<class Impl>
  38 OzoneLWLSQ<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
  39                                                  OzoneLWLSQ *lsq_ptr)
  40     : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
  41 {
  42     this->setFlags(Event::AutoDelete);
  43 }
  44
  45 template<class Impl>
  46 void
  47 OzoneLWLSQ<Impl>::WritebackEvent::process()
  48 {
  49     if (!lsqPtr->isSwitchedOut()) {
  50         lsqPtr->writeback(inst, pkt);
  51     }
  52     delete pkt;
  53 }
  54
  55 template<class Impl>
  56 const char *
  57 OzoneLWLSQ<Impl>::WritebackEvent::description() const
  58 {
  59     return "Store writeback";
  60 }
  61
  62 template <class Impl>
  63 Tick
  64 OzoneLWLSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
  65 {
  66     panic("O3CPU model does not work with atomic mode!");
  67     return curTick();
  68 }
  69
  70 template <class Impl>
  71 void
  72 OzoneLWLSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
  73 {
  74     warn("O3CPU doesn't update things on a recvFunctional");
  75 }
  76
  77 template <class Impl>
  78 bool
  79 OzoneLWLSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
  80 {
  81     lsq->completeDataAccess(pkt);
  82     return true;
  83 }
  84
  85 template <class Impl>
  86 void
  87 OzoneLWLSQ<Impl>::DcachePort::recvRetry()
  88 {
  89     lsq->recvRetry();
  90 }
  91
  92 template<class Impl>
  93 void
  94 OzoneLWLSQ<Impl>::completeDataAccess(PacketPtr pkt)
  95 {
  96     LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
  97     DynInstPtr inst = state->inst;
  98     DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
  99     DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
 100
 101     //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
 102
 103     if (isSwitchedOut() || inst->isSquashed()) {
 104         delete state;
 105         delete pkt;
 106         return;
 107     } else {
 108         if (!state->noWB) {
 109             writeback(inst, pkt);
 110         }
 111
 112         if (inst->isStore()) {
 113             completeStore(inst);
 114         }
 115     }
 116
 117     delete state;
 118     delete pkt;
 119 }
 120
 121 template <class Impl>
 122 OzoneLWLSQ<Impl>::OzoneLWLSQ()
 123     : switchedOut(false), dcachePort(this), loads(0), stores(0),
 124       storesToWB(0), storesInFlight(0), stalled(false), isStoreBlocked(false),
 125       isLoadBlocked(false), loadBlockedHandled(false)
 126 {
 127 }
 128
 129 template<class Impl>
 130 void
 131 OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
 132                        unsigned maxSQEntries, unsigned id)
 133 {
 134     DPRINTF(OzoneLSQ, "Creating OzoneLWLSQ%i object.\n",id);
 135
 136     lsqID = id;
 137
 138     LQEntries = maxLQEntries;
 139     SQEntries = maxSQEntries;
 140
 141     for (int i = 0; i < LQEntries * 2; i++) {
 142         LQIndices.push(i);
 143         SQIndices.push(i);
 144     }
 145
 146     usedPorts = 0;
 147     cachePorts = params->cachePorts;
 148
 149     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 150
 151     blockedLoadSeqNum = 0;
 152 }
 153
 154 template<class Impl>
 155 std::string
 156 OzoneLWLSQ<Impl>::name() const
 157 {
 158     return "lsqunit";
 159 }
 160
 161 template<class Impl>
 162 void
 163 OzoneLWLSQ<Impl>::regStats()
 164 {
 165     lsqMemOrderViolation
 166         .name(name() + ".memOrderViolation")
 167         .desc("Number of memory ordering violations");
 168 }
 169
 170 template<class Impl>
 171 void
 172 OzoneLWLSQ<Impl>::setCPU(OzoneCPU *cpu_ptr)
 173 {
 174     cpu = cpu_ptr;
 175     dcachePort.setName(this->name() + "-dport");
 176
 177     if (cpu->checker) {
 178         cpu->checker->setDcachePort(&dcachePort);
 179     }
 180 }
 181
 182 template<class Impl>
 183 void
 184 OzoneLWLSQ<Impl>::clearLQ()
 185 {
 186     loadQueue.clear();
 187 }
 188
 189 template<class Impl>
 190 void
 191 OzoneLWLSQ<Impl>::clearSQ()
 192 {
 193     storeQueue.clear();
 194 }
 195 /*
 196 template<class Impl>
 197 void
 198 OzoneLWLSQ<Impl>::setPageTable(PageTable *pt_ptr)
 199 {
 200     DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
 201     pTable = pt_ptr;
 202 }
 203 */
 204 template<class Impl>
 205 void
 206 OzoneLWLSQ<Impl>::resizeLQ(unsigned size)
 207 {
 208     assert( size >= LQEntries);
 209
 210     if (size > LQEntries) {
 211         while (size > loadQueue.size()) {
 212             DynInstPtr dummy;
 213             loadQueue.push_back(dummy);
 214             LQEntries++;
 215         }
 216     } else {
 217         LQEntries = size;
 218     }
 219
 220 }
 221
 222 template<class Impl>
 223 void
 224 OzoneLWLSQ<Impl>::resizeSQ(unsigned size)
 225 {
 226     if (size > SQEntries) {
 227         while (size > storeQueue.size()) {
 228             SQEntry dummy;
 229             storeQueue.push_back(dummy);
 230             SQEntries++;
 231         }
 232     } else {
 233         SQEntries = size;
 234     }
 235 }
 236
 237 template <class Impl>
 238 void
 239 OzoneLWLSQ<Impl>::insert(DynInstPtr &inst)
 240 {
 241     // Make sure we really have a memory reference.
 242     assert(inst->isMemRef());
 243
 244     // Make sure it's one of the two classes of memory references.
 245     assert(inst->isLoad() || inst->isStore());
 246
 247     if (inst->isLoad()) {
 248         insertLoad(inst);
 249     } else {
 250         insertStore(inst);
 251     }
 252 }
 253
 254 template <class Impl>
 255 void
 256 OzoneLWLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
 257 {
 258     assert(loads < LQEntries * 2);
 259     assert(!LQIndices.empty());
 260     int load_index = LQIndices.front();
 261     LQIndices.pop();
 262
 263     DPRINTF(OzoneLSQ, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
 264             load_inst->readPC(), load_index, load_inst->seqNum);
 265
 266     load_inst->lqIdx = load_index;
 267
 268     loadQueue.push_front(load_inst);
 269     LQItHash[load_index] = loadQueue.begin();
 270
 271     ++loads;
 272 }
 273
 274 template <class Impl>
 275 void
 276 OzoneLWLSQ<Impl>::insertStore(DynInstPtr &store_inst)
 277 {
 278     // Make sure it is not full before inserting an instruction.
 279     assert(stores - storesToWB < SQEntries);
 280
 281     assert(!SQIndices.empty());
 282     int store_index = SQIndices.front();
 283     SQIndices.pop();
 284
 285     DPRINTF(OzoneLSQ, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
 286             store_inst->readPC(), store_index, store_inst->seqNum);
 287
 288     store_inst->sqIdx = store_index;
 289     SQEntry entry(store_inst);
 290     if (loadQueue.empty()) {
 291         entry.lqIt = loadQueue.end();
 292     } else {
 293         entry.lqIt = loadQueue.begin();
 294     }
 295     storeQueue.push_front(entry);
 296
 297     SQItHash[store_index] = storeQueue.begin();
 298
 299     ++stores;
 300 }
 301
 302 template <class Impl>
 303 typename Impl::DynInstPtr
 304 OzoneLWLSQ<Impl>::getMemDepViolator()
 305 {
 306     DynInstPtr temp = memDepViolator;
 307
 308     memDepViolator = NULL;
 309
 310     return temp;
 311 }
 312
 313 template <class Impl>
 314 unsigned
 315 OzoneLWLSQ<Impl>::numFreeEntries()
 316 {
 317     unsigned free_lq_entries = LQEntries - loads;
 318     unsigned free_sq_entries = SQEntries - (stores + storesInFlight);
 319
 320     // Both the LQ and SQ entries have an extra dummy entry to differentiate
 321     // empty/full conditions.  Subtract 1 from the free entries.
 322     if (free_lq_entries < free_sq_entries) {
 323         return free_lq_entries - 1;
 324     } else {
 325         return free_sq_entries - 1;
 326     }
 327 }
 328
 329 template <class Impl>
 330 int
 331 OzoneLWLSQ<Impl>::numLoadsReady()
 332 {
 333     int retval = 0;
 334     LQIt lq_it = loadQueue.begin();
 335     LQIt end_it = loadQueue.end();
 336
 337     while (lq_it != end_it) {
 338         if ((*lq_it)->readyToIssue()) {
 339             ++retval;
 340         }
 341     }
 342
 343     return retval;
 344 }
 345
 346 template <class Impl>
 347 Fault
 348 OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst)
 349 {
 350     // Execute a specific load.
 351     Fault load_fault = NoFault;
 352
 353     DPRINTF(OzoneLSQ, "Executing load PC %#x, [sn:%lli]\n",
 354             inst->readPC(),inst->seqNum);
 355
 356     // Make sure it's really in the list.
 357     // Normally it should always be in the list.  However,
 358     /* due to a syscall it may not be the list.
 359 #ifdef DEBUG
 360     int i = loadHead;
 361     while (1) {
 362         if (i == loadTail && !find(inst)) {
 363             assert(0 && "Load not in the queue!");
 364         } else if (loadQueue[i] == inst) {
 365             break;
 366         }
 367
 368         i = i + 1;
 369         if (i >= LQEntries) {
 370             i = 0;
 371         }
 372     }
 373 #endif // DEBUG*/
 374
 375     load_fault = inst->initiateAcc();
 376
 377     // Might want to make sure that I'm not overwriting a previously faulting
 378     // instruction that hasn't been checked yet.
 379     // Actually probably want the oldest faulting load
 380     if (load_fault != NoFault) {
 381         DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum);
 382         if (!(inst->req->isUncacheable() && !inst->isAtCommit())) {
 383             inst->setExecuted();
 384         }
 385         // Maybe just set it as can commit here, although that might cause
 386         // some other problems with sending traps to the ROB too quickly.
 387         be->instToCommit(inst);
 388 //        iewStage->activityThisCycle();
 389     }
 390
 391     return load_fault;
 392 }
 393
 394 template <class Impl>
 395 Fault
 396 OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
 397 {
 398     // Make sure that a store exists.
 399     assert(stores != 0);
 400
 401     int store_idx = store_inst->sqIdx;
 402     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 403     assert(sq_hash_it != SQItHash.end());
 404     DPRINTF(OzoneLSQ, "Executing store PC %#x [sn:%lli]\n",
 405             store_inst->readPC(), store_inst->seqNum);
 406
 407     SQIt sq_it = (*sq_hash_it).second;
 408
 409     Fault store_fault = store_inst->initiateAcc();
 410
 411     // Store size should now be available.  Use it to get proper offset for
 412     // addr comparisons.
 413     int size = (*sq_it).size;
 414
 415     if (size == 0) {
 416         DPRINTF(OzoneLSQ,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
 417                 store_inst->readPC(),store_inst->seqNum);
 418
 419         return store_fault;
 420     }
 421
 422     assert(store_fault == NoFault);
 423
 424     if (!storeFaultInst) {
 425         if (store_fault != NoFault) {
 426             panic("Fault in a store instruction!");
 427             storeFaultInst = store_inst;
 428         } else if (store_inst->isStoreConditional()) {
 429             // Store conditionals need to set themselves as able to
 430             // writeback if we haven't had a fault by here.
 431             (*sq_it).canWB = true;
 432
 433             ++storesToWB;
 434             DPRINTF(OzoneLSQ, "Nonspeculative store! storesToWB:%i\n",
 435                     storesToWB);
 436         }
 437     }
 438
 439     LQIt lq_it = --(loadQueue.end());
 440
 441     if (!memDepViolator) {
 442         while (lq_it != loadQueue.end()) {
 443             if ((*lq_it)->seqNum < store_inst->seqNum) {
 444                 lq_it--;
 445                 continue;
 446             }
 447             // Actually should only check loads that have actually executed
 448             // Might be safe because effAddr is set to InvalAddr when the
 449             // dyn inst is created.
 450
 451             // Must actually check all addrs in the proper size range
 452             // Which is more correct than needs to be.  What if for now we just
 453             // assume all loads are quad-word loads, and do the addr based
 454             // on that.
 455             // @todo: Fix this, magic number being used here
 456             if (((*lq_it)->effAddr >> 8) ==
 457                 (store_inst->effAddr >> 8)) {
 458                 // A load incorrectly passed this store.  Squash and refetch.
 459                 // For now return a fault to show that it was unsuccessful.
 460                 memDepViolator = (*lq_it);
 461                 ++lsqMemOrderViolation;
 462
 463                 return TheISA::genMachineCheckFault();
 464             }
 465
 466             lq_it--;
 467         }
 468
 469         // If we've reached this point, there was no violation.
 470         memDepViolator = NULL;
 471     }
 472
 473     return store_fault;
 474 }
 475
 476 template <class Impl>
 477 void
 478 OzoneLWLSQ<Impl>::commitLoad()
 479 {
 480     assert(!loadQueue.empty());
 481
 482     DPRINTF(OzoneLSQ, "[sn:%lli] Committing head load instruction, PC %#x\n",
 483             loadQueue.back()->seqNum, loadQueue.back()->readPC());
 484
 485     LQIndices.push(loadQueue.back()->lqIdx);
 486     LQItHash.erase(loadQueue.back()->lqIdx);
 487
 488     loadQueue.pop_back();
 489
 490     --loads;
 491 }
 492
 493 template <class Impl>
 494 void
 495 OzoneLWLSQ<Impl>::commitLoads(InstSeqNum &youngest_inst)
 496 {
 497     assert(loads == 0 || !loadQueue.empty());
 498
 499     while (loads != 0 &&
 500            loadQueue.back()->seqNum <= youngest_inst) {
 501         commitLoad();
 502     }
 503 }
 504
 505 template <class Impl>
 506 void
 507 OzoneLWLSQ<Impl>::commitStores(InstSeqNum &youngest_inst)
 508 {
 509     assert(stores == 0 || !storeQueue.empty());
 510
 511     SQIt sq_it = --(storeQueue.end());
 512     while (!storeQueue.empty() && sq_it != storeQueue.end()) {
 513         assert((*sq_it).inst);
 514         if (!(*sq_it).canWB) {
 515             if ((*sq_it).inst->seqNum > youngest_inst) {
 516                 break;
 517             }
 518             ++storesToWB;
 519
 520             DPRINTF(OzoneLSQ, "Marking store as able to write back, PC "
 521                     "%#x [sn:%lli], storesToWB:%i\n",
 522                     (*sq_it).inst->readPC(),
 523                     (*sq_it).inst->seqNum,
 524                     storesToWB);
 525
 526             (*sq_it).canWB = true;
 527         }
 528
 529         sq_it--;
 530     }
 531 }
 532
 533 template <class Impl>
 534 void
 535 OzoneLWLSQ<Impl>::writebackStores()
 536 {
 537     SQIt sq_it = --(storeQueue.end());
 538     while (storesToWB > 0 &&
 539            sq_it != storeQueue.end() &&
 540            (*sq_it).inst &&
 541            (*sq_it).canWB &&
 542            usedPorts < cachePorts) {
 543
 544         if (isStoreBlocked) {
 545             DPRINTF(OzoneLSQ, "Unable to write back any more stores, cache"
 546                     " is blocked!\n");
 547             break;
 548         }
 549
 550         DynInstPtr inst = (*sq_it).inst;
 551
 552         if ((*sq_it).size == 0 && !(*sq_it).completed) {
 553             sq_it--;
 554             removeStore(inst->sqIdx);
 555             completeStore(inst);
 556             continue;
 557         }
 558
 559         if (inst->isDataPrefetch() || (*sq_it).committed) {
 560             sq_it--;
 561             continue;
 562         }
 563
 564         ++usedPorts;
 565
 566         assert((*sq_it).req);
 567         assert(!(*sq_it).committed);
 568
 569         Request *req = (*sq_it).req;
 570         (*sq_it).committed = true;
 571
 572         assert(!inst->memData);
 573         inst->memData = new uint8_t[64];
 574         memcpy(inst->memData, (uint8_t *)&(*sq_it).data,
 575                req->getSize());
 576
 577         MemCmd command =
 578             req->isSwap() ? MemCmd::SwapReq :
 579             (req->isLLSC() ? MemCmd::WriteReq : MemCmd::StoreCondReq);
 580         PacketPtr data_pkt = new Packet(req, command, Packet::Broadcast);
 581         data_pkt->dataStatic(inst->memData);
 582
 583         LSQSenderState *state = new LSQSenderState;
 584         state->isLoad = false;
 585         state->idx = inst->sqIdx;
 586         state->inst = inst;
 587         data_pkt->senderState = state;
 588
 589         DPRINTF(OzoneLSQ, "D-Cache: Writing back store PC:%#x "
 590                 "to Addr:%#x, data:%#x [sn:%lli]\n",
 591                 (*sq_it).inst->readPC(),
 592                 req->getPaddr(), *(inst->memData),
 593                 inst->seqNum);
 594
 595         // @todo: Remove this SC hack once the memory system handles it.
 596         if (req->isLLSC()) {
 597             if (req->isUncacheable()) {
 598                 req->setExtraData(2);
 599             } else {
 600                 if (cpu->lockFlag) {
 601                     req->setExtraData(1);
 602                 } else {
 603                     req->setExtraData(0);
 604                     // Hack: Instantly complete this store.
 605                     completeDataAccess(data_pkt);
 606                     --sq_it;
 607                     continue;
 608                 }
 609             }
 610         } else {
 611             // Non-store conditionals do not need a writeback.
 612             state->noWB = true;
 613         }
 614
 615         if (!dcachePort.sendTiming(data_pkt)) {
 616             // Need to handle becoming blocked on a store.
 617             isStoreBlocked = true;
 618             assert(retryPkt == NULL);
 619             retryPkt = data_pkt;
 620         } else {
 621             storePostSend(data_pkt, inst);
 622             --sq_it;
 623         }
 624 /*
 625         DPRINTF(OzoneLSQ, "D-Cache: Writing back store idx:%i PC:%#x "
 626                 "to Addr:%#x, data:%#x [sn:%lli]\n",
 627                 inst->sqIdx,inst->readPC(),
 628                 req->paddr, *(req->data),
 629                 inst->seqNum);
 630         DPRINTF(OzoneLSQ, "StoresInFlight: %i\n",
 631                 storesInFlight + 1);
 632
 633         if (dcacheInterface) {
 634             assert(!req->completionEvent);
 635             StoreCompletionEvent *store_event = new
 636                 StoreCompletionEvent(inst, be, NULL, this);
 637             req->completionEvent = store_event;
 638
 639             MemAccessResult result = dcacheInterface->access(req);
 640
 641             if (isStalled() &&
 642                 inst->seqNum == stallingStoreIsn) {
 643                 DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 644                         "load [sn:%lli]\n",
 645                         stallingStoreIsn, (*stallingLoad)->seqNum);
 646                 stalled = false;
 647                 stallingStoreIsn = 0;
 648                 be->replayMemInst((*stallingLoad));
 649             }
 650
 651             if (result != MA_HIT && dcacheInterface->doEvents()) {
 652                 store_event->miss = true;
 653                 typename BackEnd::LdWritebackEvent *wb = NULL;
 654                 if (req->isLLSC()) {
 655                     wb = new typename BackEnd::LdWritebackEvent(inst,
 656                                                             be);
 657                     store_event->wbEvent = wb;
 658                 }
 659
 660                 DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
 661
 662 //                DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
 663 //                        inst->seqNum);
 664
 665                 be->addDcacheMiss(inst);
 666
 667                 lastDcacheStall = curTick();
 668
 669                 _status = DcacheMissStall;
 670
 671                 // Increment stat here or something
 672
 673                 sq_it--;
 674             } else {
 675                 DPRINTF(OzoneLSQ,"D-Cache: Write Hit on idx:%i !\n",
 676                         inst->sqIdx);
 677
 678 //                DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 679 //                        inst->seqNum);
 680
 681                 if (req->isLLSC()) {
 682                     // Stx_C does not generate a system port
 683                     // transaction in the 21264, but that might be
 684                     // hard to accomplish in this model.
 685
 686                     typename BackEnd::LdWritebackEvent *wb =
 687                         new typename BackEnd::LdWritebackEvent(inst,
 688                                                                be);
 689                     store_event->wbEvent = wb;
 690                 }
 691                 sq_it--;
 692             }
 693             ++storesInFlight;
 694 //            removeStore(inst->sqIdx);
 695         } else {
 696             panic("Must HAVE DCACHE!!!!!\n");
 697         }
 698 */
 699     }
 700
 701     // Not sure this should set it to 0.
 702     usedPorts = 0;
 703
 704     assert(stores >= 0 && storesToWB >= 0);
 705 }
 706
 707 template <class Impl>
 708 void
 709 OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
 710 {
 711     DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
 712             "(Loads:%i Stores:%i)\n",squashed_num,loads,stores+storesInFlight);
 713
 714
 715     LQIt lq_it = loadQueue.begin();
 716
 717     while (loads != 0 && (*lq_it)->seqNum > squashed_num) {
 718         assert(!loadQueue.empty());
 719         // Clear the smart pointer to make sure it is decremented.
 720         DPRINTF(OzoneLSQ,"Load Instruction PC %#x squashed, "
 721                 "[sn:%lli]\n",
 722                 (*lq_it)->readPC(),
 723                 (*lq_it)->seqNum);
 724
 725         if (isStalled() && lq_it == stallingLoad) {
 726             stalled = false;
 727             stallingStoreIsn = 0;
 728             stallingLoad = NULL;
 729         }
 730
 731         --loads;
 732
 733         // Inefficient!
 734         LQHashIt lq_hash_it = LQItHash.find((*lq_it)->lqIdx);
 735         assert(lq_hash_it != LQItHash.end());
 736         LQItHash.erase(lq_hash_it);
 737         LQIndices.push((*lq_it)->lqIdx);
 738         loadQueue.erase(lq_it++);
 739     }
 740
 741     if (isLoadBlocked) {
 742         if (squashed_num < blockedLoadSeqNum) {
 743             isLoadBlocked = false;
 744             loadBlockedHandled = false;
 745             blockedLoadSeqNum = 0;
 746         }
 747     }
 748
 749     SQIt sq_it = storeQueue.begin();
 750
 751     while (stores != 0 && (*sq_it).inst->seqNum > squashed_num) {
 752         assert(!storeQueue.empty());
 753
 754         if ((*sq_it).canWB) {
 755             break;
 756         }
 757
 758         // Clear the smart pointer to make sure it is decremented.
 759         DPRINTF(OzoneLSQ,"Store Instruction PC %#x idx:%i squashed [sn:%lli]\n",
 760                 (*sq_it).inst->readPC(), (*sq_it).inst->sqIdx,
 761                 (*sq_it).inst->seqNum);
 762
 763         // I don't think this can happen.  It should have been cleared by the
 764         // stalling load.
 765         if (isStalled() &&
 766             (*sq_it).inst->seqNum == stallingStoreIsn) {
 767             panic("Is stalled should have been cleared by stalling load!\n");
 768             stalled = false;
 769             stallingStoreIsn = 0;
 770         }
 771
 772         SQHashIt sq_hash_it = SQItHash.find((*sq_it).inst->sqIdx);
 773         assert(sq_hash_it != SQItHash.end());
 774         SQItHash.erase(sq_hash_it);
 775         SQIndices.push((*sq_it).inst->sqIdx);
 776         (*sq_it).inst = NULL;
 777         (*sq_it).canWB = 0;
 778         (*sq_it).req = NULL;
 779         --stores;
 780         storeQueue.erase(sq_it++);
 781     }
 782 }
 783
 784 template <class Impl>
 785 void
 786 OzoneLWLSQ<Impl>::dumpInsts()
 787 {
 788     cprintf("Load store queue: Dumping instructions.\n");
 789     cprintf("Load queue size: %i\n", loads);
 790     cprintf("Load queue: ");
 791
 792     LQIt lq_it = --(loadQueue.end());
 793
 794     while (lq_it != loadQueue.end() && (*lq_it)) {
 795         cprintf("[sn:%lli] %#x ", (*lq_it)->seqNum,
 796                 (*lq_it)->readPC());
 797
 798         lq_it--;
 799     }
 800
 801     cprintf("\nStore queue size: %i\n", stores);
 802     cprintf("Store queue: ");
 803
 804     SQIt sq_it = --(storeQueue.end());
 805
 806     while (sq_it != storeQueue.end() && (*sq_it).inst) {
 807         cprintf("[sn:%lli]\nPC:%#x\nSize:%i\nCommitted:%i\nCompleted:%i\ncanWB:%i\n",
 808                 (*sq_it).inst->seqNum,
 809                 (*sq_it).inst->readPC(),
 810                 (*sq_it).size,
 811                 (*sq_it).committed,
 812                 (*sq_it).completed,
 813                 (*sq_it).canWB);
 814
 815         sq_it--;
 816     }
 817
 818     cprintf("\n");
 819 }
 820
 821 template <class Impl>
 822 void
 823 OzoneLWLSQ<Impl>::storePostSend(PacketPtr pkt, DynInstPtr &inst)
 824 {
 825     if (isStalled() &&
 826         inst->seqNum == stallingStoreIsn) {
 827         DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 828                 "load [sn:%lli]\n",
 829                 stallingStoreIsn, (*stallingLoad)->seqNum);
 830         stalled = false;
 831         stallingStoreIsn = 0;
 832         be->replayMemInst((*stallingLoad));
 833     }
 834
 835     if (!inst->isStoreConditional()) {
 836         // The store is basically completed at this time. This
 837         // only works so long as the checker doesn't try to
 838         // verify the value in memory for stores.
 839         inst->setCompleted();
 840         if (cpu->checker) {
 841             cpu->checker->verify(inst);
 842         }
 843     }
 844 }
 845
 846 template <class Impl>
 847 void
 848 OzoneLWLSQ<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
 849 {
 850     // Squashed instructions do not need to complete their access.
 851     if (inst->isSquashed()) {
 852         assert(!inst->isStore());
 853         return;
 854     }
 855
 856     if (!inst->isExecuted()) {
 857         inst->setExecuted();
 858
 859         // Complete access to copy data to proper place.
 860         inst->completeAcc(pkt);
 861     }
 862
 863     // Need to insert instruction into queue to commit
 864     be->instToCommit(inst);
 865 }
 866
 867 template <class Impl>
 868 void
 869 OzoneLWLSQ<Impl>::removeStore(int store_idx)
 870 {
 871     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 872     assert(sq_hash_it != SQItHash.end());
 873     SQIt sq_it = (*sq_hash_it).second;
 874
 875     assert((*sq_it).inst);
 876     (*sq_it).completed = true;
 877     DynInstPtr inst = (*sq_it).inst;
 878
 879     if (isStalled() &&
 880         inst->seqNum == stallingStoreIsn) {
 881         DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 882                 "load [sn:%lli]\n",
 883                 stallingStoreIsn, (*stallingLoad)->seqNum);
 884         stalled = false;
 885         stallingStoreIsn = 0;
 886         be->replayMemInst((*stallingLoad));
 887     }
 888
 889     DPRINTF(OzoneLSQ, "Completing store idx:%i [sn:%lli], storesToWB:%i\n",
 890             inst->sqIdx, inst->seqNum, storesToWB);
 891
 892     assert(!storeQueue.empty());
 893     SQItHash.erase(sq_hash_it);
 894     SQIndices.push(inst->sqIdx);
 895     storeQueue.erase(sq_it);
 896 }
 897
 898 template <class Impl>
 899 void
 900 OzoneLWLSQ<Impl>::completeStore(DynInstPtr &inst)
 901 {
 902     --storesToWB;
 903     --stores;
 904
 905     inst->setCompleted();
 906     if (cpu->checker) {
 907         cpu->checker->verify(inst);
 908     }
 909 }
 910
 911 template <class Impl>
 912 void
 913 OzoneLWLSQ<Impl>::recvRetry()
 914 {
 915     panic("Unimplemented!");
 916 }
 917
 918 template <class Impl>
 919 void
 920 OzoneLWLSQ<Impl>::switchOut()
 921 {
 922     assert(storesToWB == 0);
 923     switchedOut = true;
 924
 925     // Clear the queue to free up resources
 926     assert(stores == 0);
 927     assert(storeQueue.empty());
 928     assert(loads == 0);
 929     assert(loadQueue.empty());
 930     assert(storesInFlight == 0);
 931     storeQueue.clear();
 932     loadQueue.clear();
 933     loads = stores = storesToWB = storesInFlight = 0;
 934 }
 935
 936 template <class Impl>
 937 void
 938 OzoneLWLSQ<Impl>::takeOverFrom(ThreadContext *old_tc)
 939 {
 940     // Clear out any old state. May be redundant if this is the first time
 941     // the CPU is being used.
 942     stalled = false;
 943     isLoadBlocked = false;
 944     loadBlockedHandled = false;
 945     switchedOut = false;
 946
 947     // Could do simple checks here to see if indices are on twice
 948     while (!LQIndices.empty())
 949         LQIndices.pop();
 950     while (!SQIndices.empty())
 951         SQIndices.pop();
 952
 953     for (int i = 0; i < LQEntries * 2; i++) {
 954         LQIndices.push(i);
 955         SQIndices.push(i);
 956     }
 957
 958     usedPorts = 0;
 959
 960     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 961
 962     blockedLoadSeqNum = 0;
 963 }