src/cpu/ozone/lw_lsq_impl.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "config/use_checker.hh"
  32
  33 #include "arch/isa_traits.hh"
  34 #include "base/str.hh"
  35 #include "cpu/ozone/lw_lsq.hh"
  36 #include "cpu/checker/cpu.hh"
  37
  38 template<class Impl>
  39 OzoneLWLSQ<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
  40                                                  OzoneLWLSQ *lsq_ptr)
  41     : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
  42 {
  43     this->setFlags(Event::AutoDelete);
  44 }
  45
  46 template<class Impl>
  47 void
  48 OzoneLWLSQ<Impl>::WritebackEvent::process()
  49 {
  50     if (!lsqPtr->isSwitchedOut()) {
  51         lsqPtr->writeback(inst, pkt);
  52     }
  53     delete pkt;
  54 }
  55
  56 template<class Impl>
  57 const char *
  58 OzoneLWLSQ<Impl>::WritebackEvent::description()
  59 {
  60     return "Store writeback event";
  61 }
  62
  63 template <class Impl>
  64 Tick
  65 OzoneLWLSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
  66 {
  67     panic("O3CPU model does not work with atomic mode!");
  68     return curTick;
  69 }
  70
  71 template <class Impl>
  72 void
  73 OzoneLWLSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
  74 {
  75     panic("O3CPU doesn't expect recvFunctional callback!");
  76 }
  77
  78 template <class Impl>
  79 void
  80 OzoneLWLSQ<Impl>::DcachePort::recvStatusChange(Status status)
  81 {
  82     if (status == RangeChange)
  83         return;
  84
  85     panic("O3CPU doesn't expect recvStatusChange callback!");
  86 }
  87
  88 template <class Impl>
  89 bool
  90 OzoneLWLSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
  91 {
  92     lsq->completeDataAccess(pkt);
  93     return true;
  94 }
  95
  96 template <class Impl>
  97 void
  98 OzoneLWLSQ<Impl>::DcachePort::recvRetry()
  99 {
 100     lsq->recvRetry();
 101 }
 102
 103 template<class Impl>
 104 void
 105 OzoneLWLSQ<Impl>::completeDataAccess(PacketPtr pkt)
 106 {
 107     LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
 108     DynInstPtr inst = state->inst;
 109     DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
 110     DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
 111
 112     //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
 113
 114     if (isSwitchedOut() || inst->isSquashed()) {
 115         delete state;
 116         delete pkt;
 117         return;
 118     } else {
 119         if (!state->noWB) {
 120             writeback(inst, pkt);
 121         }
 122
 123         if (inst->isStore()) {
 124             completeStore(state->idx);
 125         }
 126     }
 127
 128     delete state;
 129     delete pkt;
 130 }
 131
 132 template <class Impl>
 133 OzoneLWLSQ<Impl>::OzoneLWLSQ()
 134     : switchedOut(false), dcachePort(this), loads(0), stores(0),
 135       storesToWB(0), stalled(false), isStoreBlocked(false),
 136       isLoadBlocked(false), loadBlockedHandled(false)
 137 {
 138 }
 139
 140 template<class Impl>
 141 void
 142 OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
 143                        unsigned maxSQEntries, unsigned id)
 144 {
 145     DPRINTF(OzoneLSQ, "Creating OzoneLWLSQ%i object.\n",id);
 146
 147     lsqID = id;
 148
 149     LQEntries = maxLQEntries;
 150     SQEntries = maxSQEntries;
 151
 152     for (int i = 0; i < LQEntries * 2; i++) {
 153         LQIndices.push(i);
 154         SQIndices.push(i);
 155     }
 156
 157     mem = params->mem;
 158
 159     usedPorts = 0;
 160     cachePorts = params->cachePorts;
 161
 162     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 163
 164     blockedLoadSeqNum = 0;
 165 }
 166
 167 template<class Impl>
 168 std::string
 169 OzoneLWLSQ<Impl>::name() const
 170 {
 171     return "lsqunit";
 172 }
 173
 174 template<class Impl>
 175 void
 176 OzoneLWLSQ<Impl>::setCPU(OzoneCPU *cpu_ptr)
 177 {
 178     cpu = cpu_ptr;
 179     dcachePort.setName(this->name() + "-dport");
 180
 181 #if USE_CHECKER
 182     if (cpu->checker) {
 183         cpu->checker->setDcachePort(&dcachePort);
 184     }
 185 #endif
 186 }
 187
 188 template<class Impl>
 189 void
 190 OzoneLWLSQ<Impl>::clearLQ()
 191 {
 192     loadQueue.clear();
 193 }
 194
 195 template<class Impl>
 196 void
 197 OzoneLWLSQ<Impl>::clearSQ()
 198 {
 199     storeQueue.clear();
 200 }
 201 /*
 202 template<class Impl>
 203 void
 204 OzoneLWLSQ<Impl>::setPageTable(PageTable *pt_ptr)
 205 {
 206     DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
 207     pTable = pt_ptr;
 208 }
 209 */
 210 template<class Impl>
 211 void
 212 OzoneLWLSQ<Impl>::resizeLQ(unsigned size)
 213 {
 214     assert( size >= LQEntries);
 215
 216     if (size > LQEntries) {
 217         while (size > loadQueue.size()) {
 218             DynInstPtr dummy;
 219             loadQueue.push_back(dummy);
 220             LQEntries++;
 221         }
 222     } else {
 223         LQEntries = size;
 224     }
 225
 226 }
 227
 228 template<class Impl>
 229 void
 230 OzoneLWLSQ<Impl>::resizeSQ(unsigned size)
 231 {
 232     if (size > SQEntries) {
 233         while (size > storeQueue.size()) {
 234             SQEntry dummy;
 235             storeQueue.push_back(dummy);
 236             SQEntries++;
 237         }
 238     } else {
 239         SQEntries = size;
 240     }
 241 }
 242
 243 template <class Impl>
 244 void
 245 OzoneLWLSQ<Impl>::insert(DynInstPtr &inst)
 246 {
 247     // Make sure we really have a memory reference.
 248     assert(inst->isMemRef());
 249
 250     // Make sure it's one of the two classes of memory references.
 251     assert(inst->isLoad() || inst->isStore());
 252
 253     if (inst->isLoad()) {
 254         insertLoad(inst);
 255     } else {
 256         insertStore(inst);
 257     }
 258 }
 259
 260 template <class Impl>
 261 void
 262 OzoneLWLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
 263 {
 264     assert(loads < LQEntries * 2);
 265     assert(!LQIndices.empty());
 266     int load_index = LQIndices.front();
 267     LQIndices.pop();
 268
 269     DPRINTF(OzoneLSQ, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
 270             load_inst->readPC(), load_index, load_inst->seqNum);
 271
 272     load_inst->lqIdx = load_index;
 273
 274     loadQueue.push_front(load_inst);
 275     LQItHash[load_index] = loadQueue.begin();
 276
 277     ++loads;
 278 }
 279
 280 template <class Impl>
 281 void
 282 OzoneLWLSQ<Impl>::insertStore(DynInstPtr &store_inst)
 283 {
 284     // Make sure it is not full before inserting an instruction.
 285     assert(stores - storesToWB < SQEntries);
 286
 287     assert(!SQIndices.empty());
 288     int store_index = SQIndices.front();
 289     SQIndices.pop();
 290
 291     DPRINTF(OzoneLSQ, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
 292             store_inst->readPC(), store_index, store_inst->seqNum);
 293
 294     store_inst->sqIdx = store_index;
 295     SQEntry entry(store_inst);
 296     if (loadQueue.empty()) {
 297         entry.lqIt = loadQueue.end();
 298     } else {
 299         entry.lqIt = loadQueue.begin();
 300     }
 301     storeQueue.push_front(entry);
 302
 303     SQItHash[store_index] = storeQueue.begin();
 304
 305     ++stores;
 306 }
 307
 308 template <class Impl>
 309 typename Impl::DynInstPtr
 310 OzoneLWLSQ<Impl>::getMemDepViolator()
 311 {
 312     DynInstPtr temp = memDepViolator;
 313
 314     memDepViolator = NULL;
 315
 316     return temp;
 317 }
 318
 319 template <class Impl>
 320 unsigned
 321 OzoneLWLSQ<Impl>::numFreeEntries()
 322 {
 323     unsigned free_lq_entries = LQEntries - loads;
 324     unsigned free_sq_entries = SQEntries - stores;
 325
 326     // Both the LQ and SQ entries have an extra dummy entry to differentiate
 327     // empty/full conditions.  Subtract 1 from the free entries.
 328     if (free_lq_entries < free_sq_entries) {
 329         return free_lq_entries - 1;
 330     } else {
 331         return free_sq_entries - 1;
 332     }
 333 }
 334
 335 template <class Impl>
 336 int
 337 OzoneLWLSQ<Impl>::numLoadsReady()
 338 {
 339     int retval = 0;
 340     LQIt lq_it = loadQueue.begin();
 341     LQIt end_it = loadQueue.end();
 342
 343     while (lq_it != end_it) {
 344         if ((*lq_it)->readyToIssue()) {
 345             ++retval;
 346         }
 347     }
 348
 349     return retval;
 350 }
 351
 352 template <class Impl>
 353 Fault
 354 OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst)
 355 {
 356     // Execute a specific load.
 357     Fault load_fault = NoFault;
 358
 359     DPRINTF(OzoneLSQ, "Executing load PC %#x, [sn:%lli]\n",
 360             inst->readPC(),inst->seqNum);
 361
 362     // Make sure it's really in the list.
 363     // Normally it should always be in the list.  However,
 364     /* due to a syscall it may not be the list.
 365 #ifdef DEBUG
 366     int i = loadHead;
 367     while (1) {
 368         if (i == loadTail && !find(inst)) {
 369             assert(0 && "Load not in the queue!");
 370         } else if (loadQueue[i] == inst) {
 371             break;
 372         }
 373
 374         i = i + 1;
 375         if (i >= LQEntries) {
 376             i = 0;
 377         }
 378     }
 379 #endif // DEBUG*/
 380
 381     load_fault = inst->initiateAcc();
 382
 383     // Might want to make sure that I'm not overwriting a previously faulting
 384     // instruction that hasn't been checked yet.
 385     // Actually probably want the oldest faulting load
 386     if (load_fault != NoFault) {
 387         DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum);
 388         // Maybe just set it as can commit here, although that might cause
 389         // some other problems with sending traps to the ROB too quickly.
 390         be->instToCommit(inst);
 391 //        iewStage->activityThisCycle();
 392     }
 393
 394     return load_fault;
 395 }
 396
 397 template <class Impl>
 398 Fault
 399 OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
 400 {
 401     // Make sure that a store exists.
 402     assert(stores != 0);
 403
 404     int store_idx = store_inst->sqIdx;
 405     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 406     assert(sq_hash_it != SQItHash.end());
 407     DPRINTF(OzoneLSQ, "Executing store PC %#x [sn:%lli]\n",
 408             store_inst->readPC(), store_inst->seqNum);
 409
 410     SQIt sq_it = (*sq_hash_it).second;
 411
 412     Fault store_fault = store_inst->initiateAcc();
 413
 414     // Store size should now be available.  Use it to get proper offset for
 415     // addr comparisons.
 416     int size = (*sq_it).size;
 417
 418     if (size == 0) {
 419         DPRINTF(OzoneLSQ,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
 420                 store_inst->readPC(),store_inst->seqNum);
 421
 422         return store_fault;
 423     }
 424
 425     assert(store_fault == NoFault);
 426
 427     if (!storeFaultInst) {
 428         if (store_fault != NoFault) {
 429             panic("Fault in a store instruction!");
 430             storeFaultInst = store_inst;
 431         } else if (store_inst->isStoreConditional()) {
 432             // Store conditionals need to set themselves as able to
 433             // writeback if we haven't had a fault by here.
 434             (*sq_it).canWB = true;
 435
 436             ++storesToWB;
 437             DPRINTF(OzoneLSQ, "Nonspeculative store! storesToWB:%i\n",
 438                     storesToWB);
 439         }
 440     }
 441
 442     LQIt lq_it = --(loadQueue.end());
 443
 444     if (!memDepViolator) {
 445         while (lq_it != loadQueue.end()) {
 446             if ((*lq_it)->seqNum < store_inst->seqNum) {
 447                 lq_it--;
 448                 continue;
 449             }
 450             // Actually should only check loads that have actually executed
 451             // Might be safe because effAddr is set to InvalAddr when the
 452             // dyn inst is created.
 453
 454             // Must actually check all addrs in the proper size range
 455             // Which is more correct than needs to be.  What if for now we just
 456             // assume all loads are quad-word loads, and do the addr based
 457             // on that.
 458             // @todo: Fix this, magic number being used here
 459             if (((*lq_it)->effAddr >> 8) ==
 460                 (store_inst->effAddr >> 8)) {
 461                 // A load incorrectly passed this store.  Squash and refetch.
 462                 // For now return a fault to show that it was unsuccessful.
 463                 memDepViolator = (*lq_it);
 464
 465                 return TheISA::genMachineCheckFault();
 466             }
 467
 468             lq_it--;
 469         }
 470
 471         // If we've reached this point, there was no violation.
 472         memDepViolator = NULL;
 473     }
 474
 475     return store_fault;
 476 }
 477
 478 template <class Impl>
 479 void
 480 OzoneLWLSQ<Impl>::commitLoad()
 481 {
 482     assert(!loadQueue.empty());
 483
 484     DPRINTF(OzoneLSQ, "[sn:%lli] Committing head load instruction, PC %#x\n",
 485             loadQueue.back()->seqNum, loadQueue.back()->readPC());
 486
 487     LQIndices.push(loadQueue.back()->lqIdx);
 488     LQItHash.erase(loadQueue.back()->lqIdx);
 489
 490     loadQueue.pop_back();
 491
 492     --loads;
 493 }
 494
 495 template <class Impl>
 496 void
 497 OzoneLWLSQ<Impl>::commitLoads(InstSeqNum &youngest_inst)
 498 {
 499     assert(loads == 0 || !loadQueue.empty());
 500
 501     while (loads != 0 &&
 502            loadQueue.back()->seqNum <= youngest_inst) {
 503         commitLoad();
 504     }
 505 }
 506
 507 template <class Impl>
 508 void
 509 OzoneLWLSQ<Impl>::commitStores(InstSeqNum &youngest_inst)
 510 {
 511     assert(stores == 0 || !storeQueue.empty());
 512
 513     SQIt sq_it = --(storeQueue.end());
 514     while (!storeQueue.empty() && sq_it != storeQueue.end()) {
 515         assert((*sq_it).inst);
 516         if (!(*sq_it).canWB) {
 517             if ((*sq_it).inst->seqNum > youngest_inst) {
 518                 break;
 519             }
 520             ++storesToWB;
 521
 522             DPRINTF(OzoneLSQ, "Marking store as able to write back, PC "
 523                     "%#x [sn:%lli], storesToWB:%i\n",
 524                     (*sq_it).inst->readPC(),
 525                     (*sq_it).inst->seqNum,
 526                     storesToWB);
 527
 528             (*sq_it).canWB = true;
 529         }
 530
 531         sq_it--;
 532     }
 533 }
 534
 535 template <class Impl>
 536 void
 537 OzoneLWLSQ<Impl>::writebackStores()
 538 {
 539     SQIt sq_it = --(storeQueue.end());
 540     while (storesToWB > 0 &&
 541            sq_it != storeQueue.end() &&
 542            (*sq_it).inst &&
 543            (*sq_it).canWB &&
 544            usedPorts < cachePorts) {
 545
 546         if (isStoreBlocked) {
 547             DPRINTF(OzoneLSQ, "Unable to write back any more stores, cache"
 548                     " is blocked!\n");
 549             break;
 550         }
 551
 552         DynInstPtr inst = (*sq_it).inst;
 553
 554         if ((*sq_it).size == 0 && !(*sq_it).completed) {
 555             sq_it--;
 556             completeStore(inst->sqIdx);
 557
 558             continue;
 559         }
 560
 561         if (inst->isDataPrefetch() || (*sq_it).committed) {
 562             sq_it--;
 563             continue;
 564         }
 565
 566         ++usedPorts;
 567
 568         assert((*sq_it).req);
 569         assert(!(*sq_it).committed);
 570
 571         Request *req = (*sq_it).req;
 572         (*sq_it).committed = true;
 573
 574         assert(!inst->memData);
 575         inst->memData = new uint8_t[64];
 576         memcpy(inst->memData, (uint8_t *)&(*sq_it).data,
 577                req->getSize());
 578
 579         PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
 580         data_pkt->dataStatic(inst->memData);
 581
 582         LSQSenderState *state = new LSQSenderState;
 583         state->isLoad = false;
 584         state->idx = inst->sqIdx;
 585         state->inst = inst;
 586         data_pkt->senderState = state;
 587
 588         DPRINTF(OzoneLSQ, "D-Cache: Writing back store PC:%#x "
 589                 "to Addr:%#x, data:%#x [sn:%lli]\n",
 590                 (*sq_it).inst->readPC(),
 591                 req->getPaddr(), *(inst->memData),
 592                 inst->seqNum);
 593
 594         // @todo: Remove this SC hack once the memory system handles it.
 595         if (req->getFlags() & LOCKED) {
 596             if (req->getFlags() & UNCACHEABLE) {
 597                 req->setScResult(2);
 598             } else {
 599                 if (cpu->lockFlag) {
 600                     req->setScResult(1);
 601                 } else {
 602                     req->setScResult(0);
 603                     // Hack: Instantly complete this store.
 604                     completeDataAccess(data_pkt);
 605                     --sq_it;
 606                     continue;
 607                 }
 608             }
 609         } else {
 610             // Non-store conditionals do not need a writeback.
 611             state->noWB = true;
 612         }
 613
 614         if (!dcachePort.sendTiming(data_pkt)) {
 615             // Need to handle becoming blocked on a store.
 616             isStoreBlocked = true;
 617             assert(retryPkt == NULL);
 618             retryPkt = data_pkt;
 619         } else {
 620             storePostSend(data_pkt, inst);
 621             --sq_it;
 622         }
 623 /*
 624         DPRINTF(OzoneLSQ, "D-Cache: Writing back store idx:%i PC:%#x "
 625                 "to Addr:%#x, data:%#x [sn:%lli]\n",
 626                 inst->sqIdx,inst->readPC(),
 627                 req->paddr, *(req->data),
 628                 inst->seqNum);
 629
 630         if (dcacheInterface) {
 631             assert(!req->completionEvent);
 632             StoreCompletionEvent *store_event = new
 633                 StoreCompletionEvent(inst, be, NULL, this);
 634             req->completionEvent = store_event;
 635
 636             MemAccessResult result = dcacheInterface->access(req);
 637
 638             if (isStalled() &&
 639                 inst->seqNum == stallingStoreIsn) {
 640                 DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 641                         "load [sn:%lli]\n",
 642                         stallingStoreIsn, (*stallingLoad)->seqNum);
 643                 stalled = false;
 644                 stallingStoreIsn = 0;
 645                 be->replayMemInst((*stallingLoad));
 646             }
 647
 648             if (result != MA_HIT && dcacheInterface->doEvents()) {
 649                 store_event->miss = true;
 650                 typename BackEnd::LdWritebackEvent *wb = NULL;
 651                 if (req->flags & LOCKED) {
 652                     wb = new typename BackEnd::LdWritebackEvent(inst,
 653                                                             be);
 654                     store_event->wbEvent = wb;
 655                 }
 656
 657                 DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
 658
 659 //                DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
 660 //                        inst->seqNum);
 661
 662                 be->addDcacheMiss(inst);
 663
 664                 lastDcacheStall = curTick;
 665
 666                 _status = DcacheMissStall;
 667
 668                 // Increment stat here or something
 669
 670                 sq_it--;
 671             } else {
 672                 DPRINTF(OzoneLSQ,"D-Cache: Write Hit on idx:%i !\n",
 673                         inst->sqIdx);
 674
 675 //                DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 676 //                        inst->seqNum);
 677
 678                 if (req->flags & LOCKED) {
 679                     // Stx_C does not generate a system port
 680                     // transaction in the 21264, but that might be
 681                     // hard to accomplish in this model.
 682
 683                     typename BackEnd::LdWritebackEvent *wb =
 684                         new typename BackEnd::LdWritebackEvent(inst,
 685                                                                be);
 686                     store_event->wbEvent = wb;
 687                 }
 688                 sq_it--;
 689             }
 690         } else {
 691             panic("Must HAVE DCACHE!!!!!\n");
 692         }
 693 */
 694     }
 695
 696     // Not sure this should set it to 0.
 697     usedPorts = 0;
 698
 699     assert(stores >= 0 && storesToWB >= 0);
 700 }
 701
 702 template <class Impl>
 703 void
 704 OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
 705 {
 706     DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
 707             "(Loads:%i Stores:%i)\n",squashed_num,loads,stores);
 708
 709
 710     LQIt lq_it = loadQueue.begin();
 711
 712     while (loads != 0 && (*lq_it)->seqNum > squashed_num) {
 713         assert(!loadQueue.empty());
 714         // Clear the smart pointer to make sure it is decremented.
 715         DPRINTF(OzoneLSQ,"Load Instruction PC %#x squashed, "
 716                 "[sn:%lli]\n",
 717                 (*lq_it)->readPC(),
 718                 (*lq_it)->seqNum);
 719
 720         if (isStalled() && lq_it == stallingLoad) {
 721             stalled = false;
 722             stallingStoreIsn = 0;
 723             stallingLoad = NULL;
 724         }
 725
 726         --loads;
 727
 728         // Inefficient!
 729         LQHashIt lq_hash_it = LQItHash.find((*lq_it)->lqIdx);
 730         assert(lq_hash_it != LQItHash.end());
 731         LQItHash.erase(lq_hash_it);
 732         LQIndices.push((*lq_it)->lqIdx);
 733         loadQueue.erase(lq_it++);
 734     }
 735
 736     if (isLoadBlocked) {
 737         if (squashed_num < blockedLoadSeqNum) {
 738             isLoadBlocked = false;
 739             loadBlockedHandled = false;
 740             blockedLoadSeqNum = 0;
 741         }
 742     }
 743
 744     SQIt sq_it = storeQueue.begin();
 745
 746     while (stores != 0 && (*sq_it).inst->seqNum > squashed_num) {
 747         assert(!storeQueue.empty());
 748
 749         if ((*sq_it).canWB) {
 750             break;
 751         }
 752
 753         // Clear the smart pointer to make sure it is decremented.
 754         DPRINTF(OzoneLSQ,"Store Instruction PC %#x idx:%i squashed [sn:%lli]\n",
 755                 (*sq_it).inst->readPC(), (*sq_it).inst->sqIdx,
 756                 (*sq_it).inst->seqNum);
 757
 758         // I don't think this can happen.  It should have been cleared by the
 759         // stalling load.
 760         if (isStalled() &&
 761             (*sq_it).inst->seqNum == stallingStoreIsn) {
 762             panic("Is stalled should have been cleared by stalling load!\n");
 763             stalled = false;
 764             stallingStoreIsn = 0;
 765         }
 766
 767         SQHashIt sq_hash_it = SQItHash.find((*sq_it).inst->sqIdx);
 768         assert(sq_hash_it != SQItHash.end());
 769         SQItHash.erase(sq_hash_it);
 770         SQIndices.push((*sq_it).inst->sqIdx);
 771         (*sq_it).inst = NULL;
 772         (*sq_it).canWB = 0;
 773         (*sq_it).req = NULL;
 774         --stores;
 775         storeQueue.erase(sq_it++);
 776     }
 777 }
 778
 779 template <class Impl>
 780 void
 781 OzoneLWLSQ<Impl>::dumpInsts()
 782 {
 783     cprintf("Load store queue: Dumping instructions.\n");
 784     cprintf("Load queue size: %i\n", loads);
 785     cprintf("Load queue: ");
 786
 787     LQIt lq_it = --(loadQueue.end());
 788
 789     while (lq_it != loadQueue.end() && (*lq_it)) {
 790         cprintf("[sn:%lli] %#x ", (*lq_it)->seqNum,
 791                 (*lq_it)->readPC());
 792
 793         lq_it--;
 794     }
 795
 796     cprintf("\nStore queue size: %i\n", stores);
 797     cprintf("Store queue: ");
 798
 799     SQIt sq_it = --(storeQueue.end());
 800
 801     while (sq_it != storeQueue.end() && (*sq_it).inst) {
 802         cprintf("[sn:%lli]\nPC:%#x\nSize:%i\nCommitted:%i\nCompleted:%i\ncanWB:%i\n",
 803                 (*sq_it).inst->seqNum,
 804                 (*sq_it).inst->readPC(),
 805                 (*sq_it).size,
 806                 (*sq_it).committed,
 807                 (*sq_it).completed,
 808                 (*sq_it).canWB);
 809
 810         sq_it--;
 811     }
 812
 813     cprintf("\n");
 814 }
 815
 816 template <class Impl>
 817 void
 818 OzoneLWLSQ<Impl>::storePostSend(Packet *pkt, DynInstPtr &inst)
 819 {
 820     if (isStalled() &&
 821         inst->seqNum == stallingStoreIsn) {
 822         DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 823                 "load [sn:%lli]\n",
 824                 stallingStoreIsn, (*stallingLoad)->seqNum);
 825         stalled = false;
 826         stallingStoreIsn = 0;
 827         be->replayMemInst((*stallingLoad));
 828     }
 829
 830     if (!inst->isStoreConditional()) {
 831         // The store is basically completed at this time. This
 832         // only works so long as the checker doesn't try to
 833         // verify the value in memory for stores.
 834         inst->setCompleted();
 835 #if USE_CHECKER
 836         if (cpu->checker) {
 837             cpu->checker->verify(inst);
 838         }
 839 #endif
 840     }
 841
 842     if (pkt->result != Packet::Success) {
 843         DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
 844
 845         DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
 846                 inst->seqNum);
 847
 848         //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
 849
 850         //DPRINTF(OzoneLWLSQ, "Added MSHR. count = %i\n",mshrSeqNums.size());
 851
 852         // @todo: Increment stat here.
 853     } else {
 854         DPRINTF(OzoneLSQ,"D-Cache: Write Hit!\n");
 855
 856         DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 857                 inst->seqNum);
 858     }
 859 }
 860
 861 template <class Impl>
 862 void
 863 OzoneLWLSQ<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
 864 {
 865     // Squashed instructions do not need to complete their access.
 866     if (inst->isSquashed()) {
 867         assert(!inst->isStore());
 868         return;
 869     }
 870
 871     if (!inst->isExecuted()) {
 872         inst->setExecuted();
 873
 874         // Complete access to copy data to proper place.
 875         inst->completeAcc(pkt);
 876     }
 877
 878     // Need to insert instruction into queue to commit
 879     be->instToCommit(inst);
 880 }
 881
 882 template <class Impl>
 883 void
 884 OzoneLWLSQ<Impl>::completeStore(int store_idx)
 885 {
 886     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 887     assert(sq_hash_it != SQItHash.end());
 888     SQIt sq_it = (*sq_hash_it).second;
 889
 890     assert((*sq_it).inst);
 891     (*sq_it).completed = true;
 892     DynInstPtr inst = (*sq_it).inst;
 893
 894     --storesToWB;
 895
 896     if (isStalled() &&
 897         inst->seqNum == stallingStoreIsn) {
 898         DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 899                 "load [sn:%lli]\n",
 900                 stallingStoreIsn, (*stallingLoad)->seqNum);
 901         stalled = false;
 902         stallingStoreIsn = 0;
 903         be->replayMemInst((*stallingLoad));
 904     }
 905
 906     DPRINTF(OzoneLSQ, "Completing store idx:%i [sn:%lli], storesToWB:%i\n",
 907             inst->sqIdx, inst->seqNum, storesToWB);
 908
 909     assert(!storeQueue.empty());
 910     SQItHash.erase(sq_hash_it);
 911     SQIndices.push(inst->sqIdx);
 912     storeQueue.erase(sq_it);
 913     --stores;
 914
 915     inst->setCompleted();
 916 #if USE_CHECKER
 917     if (cpu->checker) {
 918         cpu->checker->verify(inst);
 919     }
 920 #endif
 921 }
 922
 923 template <class Impl>
 924 void
 925 OzoneLWLSQ<Impl>::recvRetry()
 926 {
 927     panic("Unimplemented!");
 928 }
 929
 930 template <class Impl>
 931 void
 932 OzoneLWLSQ<Impl>::switchOut()
 933 {
 934     assert(storesToWB == 0);
 935     switchedOut = true;
 936
 937     // Clear the queue to free up resources
 938     storeQueue.clear();
 939     loadQueue.clear();
 940     loads = stores = storesToWB = 0;
 941 }
 942
 943 template <class Impl>
 944 void
 945 OzoneLWLSQ<Impl>::takeOverFrom(ThreadContext *old_tc)
 946 {
 947     // Clear out any old state. May be redundant if this is the first time
 948     // the CPU is being used.
 949     stalled = false;
 950     isLoadBlocked = false;
 951     loadBlockedHandled = false;
 952     switchedOut = false;
 953
 954     // Could do simple checks here to see if indices are on twice
 955     while (!LQIndices.empty())
 956         LQIndices.pop();
 957     while (!SQIndices.empty())
 958         SQIndices.pop();
 959
 960     for (int i = 0; i < LQEntries * 2; i++) {
 961         LQIndices.push(i);
 962         SQIndices.push(i);
 963     }
 964
 965     usedPorts = 0;
 966
 967     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 968
 969     blockedLoadSeqNum = 0;
 970 }