src/cpu/ozone/lw_lsq_impl.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "arch/isa_traits.hh"
  32 #include "base/str.hh"
  33 #include "cpu/ozone/lw_lsq.hh"
  34 #include "cpu/checker/cpu.hh"
  35
  36 template <class Impl>
  37 OzoneLWLSQ<Impl>::StoreCompletionEvent::StoreCompletionEvent(DynInstPtr &_inst,
  38                                                              BackEnd *_be,
  39                                                              Event *wb_event,
  40                                                              OzoneLWLSQ<Impl> *lsq_ptr)
  41     : Event(&mainEventQueue),
  42       inst(_inst),
  43       be(_be),
  44       wbEvent(wb_event),
  45       miss(false),
  46       lsqPtr(lsq_ptr)
  47 {
  48     this->setFlags(Event::AutoDelete);
  49 }
  50
  51 template <class Impl>
  52 void
  53 OzoneLWLSQ<Impl>::StoreCompletionEvent::process()
  54 {
  55     DPRINTF(OzoneLSQ, "Cache miss complete for store [sn:%lli]\n",
  56             inst->seqNum);
  57
  58     //lsqPtr->removeMSHR(lsqPtr->storeQueue[storeIdx].inst->seqNum);
  59
  60 //    lsqPtr->cpu->wakeCPU();
  61     if (lsqPtr->isSwitchedOut()) {
  62         if (wbEvent)
  63             delete wbEvent;
  64
  65         return;
  66     }
  67
  68     if (wbEvent) {
  69         wbEvent->process();
  70         delete wbEvent;
  71     }
  72
  73     lsqPtr->completeStore(inst->sqIdx);
  74     if (miss)
  75         be->removeDcacheMiss(inst);
  76 }
  77
  78 template <class Impl>
  79 const char *
  80 OzoneLWLSQ<Impl>::StoreCompletionEvent::description()
  81 {
  82     return "LSQ store completion event";
  83 }
  84
  85 template <class Impl>
  86 OzoneLWLSQ<Impl>::OzoneLWLSQ()
  87     : loads(0), stores(0), storesToWB(0), stalled(false), isLoadBlocked(false),
  88       loadBlockedHandled(false)
  89 {
  90 }
  91
  92 template<class Impl>
  93 void
  94 OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
  95                        unsigned maxSQEntries, unsigned id)
  96 {
  97     DPRINTF(OzoneLSQ, "Creating OzoneLWLSQ%i object.\n",id);
  98
  99     lsqID = id;
 100
 101     LQEntries = maxLQEntries;
 102     SQEntries = maxSQEntries;
 103
 104     for (int i = 0; i < LQEntries * 2; i++) {
 105         LQIndices.push(i);
 106         SQIndices.push(i);
 107     }
 108
 109     usedPorts = 0;
 110     cachePorts = params->cachePorts;
 111
 112     dcacheInterface = params->dcacheInterface;
 113
 114     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 115
 116     blockedLoadSeqNum = 0;
 117 }
 118
 119 template<class Impl>
 120 std::string
 121 OzoneLWLSQ<Impl>::name() const
 122 {
 123     return "lsqunit";
 124 }
 125
 126 template<class Impl>
 127 void
 128 OzoneLWLSQ<Impl>::clearLQ()
 129 {
 130     loadQueue.clear();
 131 }
 132
 133 template<class Impl>
 134 void
 135 OzoneLWLSQ<Impl>::clearSQ()
 136 {
 137     storeQueue.clear();
 138 }
 139 /*
 140 template<class Impl>
 141 void
 142 OzoneLWLSQ<Impl>::setPageTable(PageTable *pt_ptr)
 143 {
 144     DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
 145     pTable = pt_ptr;
 146 }
 147 */
 148 template<class Impl>
 149 void
 150 OzoneLWLSQ<Impl>::resizeLQ(unsigned size)
 151 {
 152     assert( size >= LQEntries);
 153
 154     if (size > LQEntries) {
 155         while (size > loadQueue.size()) {
 156             DynInstPtr dummy;
 157             loadQueue.push_back(dummy);
 158             LQEntries++;
 159         }
 160     } else {
 161         LQEntries = size;
 162     }
 163
 164 }
 165
 166 template<class Impl>
 167 void
 168 OzoneLWLSQ<Impl>::resizeSQ(unsigned size)
 169 {
 170     if (size > SQEntries) {
 171         while (size > storeQueue.size()) {
 172             SQEntry dummy;
 173             storeQueue.push_back(dummy);
 174             SQEntries++;
 175         }
 176     } else {
 177         SQEntries = size;
 178     }
 179 }
 180
 181 template <class Impl>
 182 void
 183 OzoneLWLSQ<Impl>::insert(DynInstPtr &inst)
 184 {
 185     // Make sure we really have a memory reference.
 186     assert(inst->isMemRef());
 187
 188     // Make sure it's one of the two classes of memory references.
 189     assert(inst->isLoad() || inst->isStore());
 190
 191     if (inst->isLoad()) {
 192         insertLoad(inst);
 193     } else {
 194         insertStore(inst);
 195     }
 196 }
 197
 198 template <class Impl>
 199 void
 200 OzoneLWLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
 201 {
 202     assert(loads < LQEntries * 2);
 203     assert(!LQIndices.empty());
 204     int load_index = LQIndices.front();
 205     LQIndices.pop();
 206
 207     DPRINTF(OzoneLSQ, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
 208             load_inst->readPC(), load_index, load_inst->seqNum);
 209
 210     load_inst->lqIdx = load_index;
 211
 212     loadQueue.push_front(load_inst);
 213     LQItHash[load_index] = loadQueue.begin();
 214
 215     ++loads;
 216 }
 217
 218 template <class Impl>
 219 void
 220 OzoneLWLSQ<Impl>::insertStore(DynInstPtr &store_inst)
 221 {
 222     // Make sure it is not full before inserting an instruction.
 223     assert(stores - storesToWB < SQEntries);
 224
 225     assert(!SQIndices.empty());
 226     int store_index = SQIndices.front();
 227     SQIndices.pop();
 228
 229     DPRINTF(OzoneLSQ, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
 230             store_inst->readPC(), store_index, store_inst->seqNum);
 231
 232     store_inst->sqIdx = store_index;
 233     SQEntry entry(store_inst);
 234     if (loadQueue.empty()) {
 235         entry.lqIt = loadQueue.end();
 236     } else {
 237         entry.lqIt = loadQueue.begin();
 238     }
 239     storeQueue.push_front(entry);
 240
 241     SQItHash[store_index] = storeQueue.begin();
 242
 243     ++stores;
 244 }
 245
 246 template <class Impl>
 247 typename Impl::DynInstPtr
 248 OzoneLWLSQ<Impl>::getMemDepViolator()
 249 {
 250     DynInstPtr temp = memDepViolator;
 251
 252     memDepViolator = NULL;
 253
 254     return temp;
 255 }
 256
 257 template <class Impl>
 258 unsigned
 259 OzoneLWLSQ<Impl>::numFreeEntries()
 260 {
 261     unsigned free_lq_entries = LQEntries - loads;
 262     unsigned free_sq_entries = SQEntries - stores;
 263
 264     // Both the LQ and SQ entries have an extra dummy entry to differentiate
 265     // empty/full conditions.  Subtract 1 from the free entries.
 266     if (free_lq_entries < free_sq_entries) {
 267         return free_lq_entries - 1;
 268     } else {
 269         return free_sq_entries - 1;
 270     }
 271 }
 272
 273 template <class Impl>
 274 int
 275 OzoneLWLSQ<Impl>::numLoadsReady()
 276 {
 277     int retval = 0;
 278     LQIt lq_it = loadQueue.begin();
 279     LQIt end_it = loadQueue.end();
 280
 281     while (lq_it != end_it) {
 282         if ((*lq_it)->readyToIssue()) {
 283             ++retval;
 284         }
 285     }
 286
 287     return retval;
 288 }
 289
 290 template <class Impl>
 291 Fault
 292 OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst)
 293 {
 294     // Execute a specific load.
 295     Fault load_fault = NoFault;
 296
 297     DPRINTF(OzoneLSQ, "Executing load PC %#x, [sn:%lli]\n",
 298             inst->readPC(),inst->seqNum);
 299
 300     // Make sure it's really in the list.
 301     // Normally it should always be in the list.  However,
 302     /* due to a syscall it may not be the list.
 303 #ifdef DEBUG
 304     int i = loadHead;
 305     while (1) {
 306         if (i == loadTail && !find(inst)) {
 307             assert(0 && "Load not in the queue!");
 308         } else if (loadQueue[i] == inst) {
 309             break;
 310         }
 311
 312         i = i + 1;
 313         if (i >= LQEntries) {
 314             i = 0;
 315         }
 316     }
 317 #endif // DEBUG*/
 318
 319     load_fault = inst->initiateAcc();
 320
 321     // Might want to make sure that I'm not overwriting a previously faulting
 322     // instruction that hasn't been checked yet.
 323     // Actually probably want the oldest faulting load
 324     if (load_fault != NoFault) {
 325         DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum);
 326         // Maybe just set it as can commit here, although that might cause
 327         // some other problems with sending traps to the ROB too quickly.
 328         be->instToCommit(inst);
 329 //        iewStage->activityThisCycle();
 330     }
 331
 332     return load_fault;
 333 }
 334
 335 template <class Impl>
 336 Fault
 337 OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
 338 {
 339     // Make sure that a store exists.
 340     assert(stores != 0);
 341
 342     int store_idx = store_inst->sqIdx;
 343     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 344     assert(sq_hash_it != SQItHash.end());
 345     DPRINTF(OzoneLSQ, "Executing store PC %#x [sn:%lli]\n",
 346             store_inst->readPC(), store_inst->seqNum);
 347
 348     SQIt sq_it = (*sq_hash_it).second;
 349
 350     Fault store_fault = store_inst->initiateAcc();
 351
 352     // Store size should now be available.  Use it to get proper offset for
 353     // addr comparisons.
 354     int size = (*sq_it).size;
 355
 356     if (size == 0) {
 357         DPRINTF(OzoneLSQ,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
 358                 store_inst->readPC(),store_inst->seqNum);
 359
 360         return store_fault;
 361     }
 362
 363     assert(store_fault == NoFault);
 364
 365     if (!storeFaultInst) {
 366         if (store_fault != NoFault) {
 367             panic("Fault in a store instruction!");
 368             storeFaultInst = store_inst;
 369         } else if (store_inst->isStoreConditional()) {
 370             // Store conditionals need to set themselves as able to
 371             // writeback if we haven't had a fault by here.
 372             (*sq_it).canWB = true;
 373
 374             ++storesToWB;
 375             DPRINTF(OzoneLSQ, "Nonspeculative store! storesToWB:%i\n",
 376                     storesToWB);
 377         }
 378     }
 379
 380     LQIt lq_it = --(loadQueue.end());
 381
 382     if (!memDepViolator) {
 383         while (lq_it != loadQueue.end()) {
 384             if ((*lq_it)->seqNum < store_inst->seqNum) {
 385                 lq_it--;
 386                 continue;
 387             }
 388             // Actually should only check loads that have actually executed
 389             // Might be safe because effAddr is set to InvalAddr when the
 390             // dyn inst is created.
 391
 392             // Must actually check all addrs in the proper size range
 393             // Which is more correct than needs to be.  What if for now we just
 394             // assume all loads are quad-word loads, and do the addr based
 395             // on that.
 396             // @todo: Fix this, magic number being used here
 397             if (((*lq_it)->effAddr >> 8) ==
 398                 (store_inst->effAddr >> 8)) {
 399                 // A load incorrectly passed this store.  Squash and refetch.
 400                 // For now return a fault to show that it was unsuccessful.
 401                 memDepViolator = (*lq_it);
 402
 403                 return TheISA::genMachineCheckFault();
 404             }
 405
 406             lq_it--;
 407         }
 408
 409         // If we've reached this point, there was no violation.
 410         memDepViolator = NULL;
 411     }
 412
 413     return store_fault;
 414 }
 415
 416 template <class Impl>
 417 void
 418 OzoneLWLSQ<Impl>::commitLoad()
 419 {
 420     assert(!loadQueue.empty());
 421
 422     DPRINTF(OzoneLSQ, "[sn:%lli] Committing head load instruction, PC %#x\n",
 423             loadQueue.back()->seqNum, loadQueue.back()->readPC());
 424
 425     LQIndices.push(loadQueue.back()->lqIdx);
 426     LQItHash.erase(loadQueue.back()->lqIdx);
 427
 428     loadQueue.pop_back();
 429
 430     --loads;
 431 }
 432
 433 template <class Impl>
 434 void
 435 OzoneLWLSQ<Impl>::commitLoads(InstSeqNum &youngest_inst)
 436 {
 437     assert(loads == 0 || !loadQueue.empty());
 438
 439     while (loads != 0 &&
 440            loadQueue.back()->seqNum <= youngest_inst) {
 441         commitLoad();
 442     }
 443 }
 444
 445 template <class Impl>
 446 void
 447 OzoneLWLSQ<Impl>::commitStores(InstSeqNum &youngest_inst)
 448 {
 449     assert(stores == 0 || !storeQueue.empty());
 450
 451     SQIt sq_it = --(storeQueue.end());
 452     while (!storeQueue.empty() && sq_it != storeQueue.end()) {
 453         assert((*sq_it).inst);
 454         if (!(*sq_it).canWB) {
 455             if ((*sq_it).inst->seqNum > youngest_inst) {
 456                 break;
 457             }
 458             ++storesToWB;
 459
 460             DPRINTF(OzoneLSQ, "Marking store as able to write back, PC "
 461                     "%#x [sn:%lli], storesToWB:%i\n",
 462                     (*sq_it).inst->readPC(),
 463                     (*sq_it).inst->seqNum,
 464                     storesToWB);
 465
 466             (*sq_it).canWB = true;
 467         }
 468
 469         sq_it--;
 470     }
 471 }
 472
 473 template <class Impl>
 474 void
 475 OzoneLWLSQ<Impl>::writebackStores()
 476 {
 477     SQIt sq_it = --(storeQueue.end());
 478     while (storesToWB > 0 &&
 479            sq_it != storeQueue.end() &&
 480            (*sq_it).inst &&
 481            (*sq_it).canWB &&
 482            usedPorts < cachePorts) {
 483
 484         DynInstPtr inst = (*sq_it).inst;
 485
 486         if ((*sq_it).size == 0 && !(*sq_it).completed) {
 487             sq_it--;
 488             completeStore(inst->sqIdx);
 489
 490             continue;
 491         }
 492
 493         if (inst->isDataPrefetch() || (*sq_it).committed) {
 494             sq_it--;
 495             continue;
 496         }
 497
 498         if (dcacheInterface && dcacheInterface->isBlocked()) {
 499             DPRINTF(OzoneLSQ, "Unable to write back any more stores, cache"
 500                     " is blocked!\n");
 501             break;
 502         }
 503
 504         ++usedPorts;
 505
 506         assert((*sq_it).req);
 507         assert(!(*sq_it).committed);
 508
 509         (*sq_it).committed = true;
 510
 511         MemReqPtr req = (*sq_it).req;
 512
 513         req->cmd = Write;
 514         req->completionEvent = NULL;
 515         req->time = curTick;
 516
 517         switch((*sq_it).size) {
 518           case 1:
 519             cpu->write(req, (uint8_t &)(*sq_it).data);
 520             break;
 521           case 2:
 522             cpu->write(req, (uint16_t &)(*sq_it).data);
 523             break;
 524           case 4:
 525             cpu->write(req, (uint32_t &)(*sq_it).data);
 526             break;
 527           case 8:
 528             cpu->write(req, (uint64_t &)(*sq_it).data);
 529             break;
 530           default:
 531             panic("Unexpected store size!\n");
 532         }
 533         if (!(req->flags & LOCKED)) {
 534             (*sq_it).inst->setCompleted();
 535             if (cpu->checker) {
 536                 cpu->checker->tick((*sq_it).inst);
 537             }
 538         }
 539
 540         DPRINTF(OzoneLSQ, "D-Cache: Writing back store idx:%i PC:%#x "
 541                 "to Addr:%#x, data:%#x [sn:%lli]\n",
 542                 inst->sqIdx,inst->readPC(),
 543                 req->paddr, *(req->data),
 544                 inst->seqNum);
 545
 546         if (dcacheInterface) {
 547             assert(!req->completionEvent);
 548             StoreCompletionEvent *store_event = new
 549                 StoreCompletionEvent(inst, be, NULL, this);
 550             req->completionEvent = store_event;
 551
 552             MemAccessResult result = dcacheInterface->access(req);
 553
 554             if (isStalled() &&
 555                 inst->seqNum == stallingStoreIsn) {
 556                 DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 557                         "load [sn:%lli]\n",
 558                         stallingStoreIsn, (*stallingLoad)->seqNum);
 559                 stalled = false;
 560                 stallingStoreIsn = 0;
 561                 be->replayMemInst((*stallingLoad));
 562             }
 563
 564             if (result != MA_HIT && dcacheInterface->doEvents()) {
 565                 store_event->miss = true;
 566                 typename BackEnd::LdWritebackEvent *wb = NULL;
 567                 if (req->flags & LOCKED) {
 568                     wb = new typename BackEnd::LdWritebackEvent(inst,
 569                                                             be);
 570                     store_event->wbEvent = wb;
 571                 }
 572
 573                 DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
 574
 575 //                DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
 576 //                        inst->seqNum);
 577
 578                 be->addDcacheMiss(inst);
 579
 580                 lastDcacheStall = curTick;
 581
 582                 _status = DcacheMissStall;
 583
 584                 // Increment stat here or something
 585
 586                 sq_it--;
 587             } else {
 588                 DPRINTF(OzoneLSQ,"D-Cache: Write Hit on idx:%i !\n",
 589                         inst->sqIdx);
 590
 591 //                DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 592 //                        inst->seqNum);
 593
 594                 if (req->flags & LOCKED) {
 595                     // Stx_C does not generate a system port
 596                     // transaction in the 21264, but that might be
 597                     // hard to accomplish in this model.
 598
 599                     typename BackEnd::LdWritebackEvent *wb =
 600                         new typename BackEnd::LdWritebackEvent(inst,
 601                                                                be);
 602                     store_event->wbEvent = wb;
 603                 }
 604                 sq_it--;
 605             }
 606         } else {
 607             panic("Must HAVE DCACHE!!!!!\n");
 608         }
 609     }
 610
 611     // Not sure this should set it to 0.
 612     usedPorts = 0;
 613
 614     assert(stores >= 0 && storesToWB >= 0);
 615 }
 616
 617 template <class Impl>
 618 void
 619 OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
 620 {
 621     DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
 622             "(Loads:%i Stores:%i)\n",squashed_num,loads,stores);
 623
 624
 625     LQIt lq_it = loadQueue.begin();
 626
 627     while (loads != 0 && (*lq_it)->seqNum > squashed_num) {
 628         assert(!loadQueue.empty());
 629         // Clear the smart pointer to make sure it is decremented.
 630         DPRINTF(OzoneLSQ,"Load Instruction PC %#x squashed, "
 631                 "[sn:%lli]\n",
 632                 (*lq_it)->readPC(),
 633                 (*lq_it)->seqNum);
 634
 635         if (isStalled() && lq_it == stallingLoad) {
 636             stalled = false;
 637             stallingStoreIsn = 0;
 638             stallingLoad = NULL;
 639         }
 640
 641         --loads;
 642
 643         // Inefficient!
 644         LQHashIt lq_hash_it = LQItHash.find((*lq_it)->lqIdx);
 645         assert(lq_hash_it != LQItHash.end());
 646         LQItHash.erase(lq_hash_it);
 647         LQIndices.push((*lq_it)->lqIdx);
 648         loadQueue.erase(lq_it++);
 649     }
 650
 651     if (isLoadBlocked) {
 652         if (squashed_num < blockedLoadSeqNum) {
 653             isLoadBlocked = false;
 654             loadBlockedHandled = false;
 655             blockedLoadSeqNum = 0;
 656         }
 657     }
 658
 659     SQIt sq_it = storeQueue.begin();
 660
 661     while (stores != 0 && (*sq_it).inst->seqNum > squashed_num) {
 662         assert(!storeQueue.empty());
 663
 664         if ((*sq_it).canWB) {
 665             break;
 666         }
 667
 668         // Clear the smart pointer to make sure it is decremented.
 669         DPRINTF(OzoneLSQ,"Store Instruction PC %#x idx:%i squashed [sn:%lli]\n",
 670                 (*sq_it).inst->readPC(), (*sq_it).inst->sqIdx,
 671                 (*sq_it).inst->seqNum);
 672
 673         // I don't think this can happen.  It should have been cleared by the
 674         // stalling load.
 675         if (isStalled() &&
 676             (*sq_it).inst->seqNum == stallingStoreIsn) {
 677             panic("Is stalled should have been cleared by stalling load!\n");
 678             stalled = false;
 679             stallingStoreIsn = 0;
 680         }
 681
 682         SQHashIt sq_hash_it = SQItHash.find((*sq_it).inst->sqIdx);
 683         assert(sq_hash_it != SQItHash.end());
 684         SQItHash.erase(sq_hash_it);
 685         SQIndices.push((*sq_it).inst->sqIdx);
 686         (*sq_it).inst = NULL;
 687         (*sq_it).canWB = 0;
 688
 689         if ((*sq_it).req) {
 690             assert(!(*sq_it).req->completionEvent);
 691         }
 692         (*sq_it).req = NULL;
 693         --stores;
 694         storeQueue.erase(sq_it++);
 695     }
 696 }
 697
 698 template <class Impl>
 699 void
 700 OzoneLWLSQ<Impl>::dumpInsts()
 701 {
 702     cprintf("Load store queue: Dumping instructions.\n");
 703     cprintf("Load queue size: %i\n", loads);
 704     cprintf("Load queue: ");
 705
 706     LQIt lq_it = --(loadQueue.end());
 707
 708     while (lq_it != loadQueue.end() && (*lq_it)) {
 709         cprintf("[sn:%lli] %#x ", (*lq_it)->seqNum,
 710                 (*lq_it)->readPC());
 711
 712         lq_it--;
 713     }
 714
 715     cprintf("\nStore queue size: %i\n", stores);
 716     cprintf("Store queue: ");
 717
 718     SQIt sq_it = --(storeQueue.end());
 719
 720     while (sq_it != storeQueue.end() && (*sq_it).inst) {
 721         cprintf("[sn:%lli]\nPC:%#x\nSize:%i\nCommitted:%i\nCompleted:%i\ncanWB:%i\n",
 722                 (*sq_it).inst->seqNum,
 723                 (*sq_it).inst->readPC(),
 724                 (*sq_it).size,
 725                 (*sq_it).committed,
 726                 (*sq_it).completed,
 727                 (*sq_it).canWB);
 728
 729         sq_it--;
 730     }
 731
 732     cprintf("\n");
 733 }
 734
 735 template <class Impl>
 736 void
 737 OzoneLWLSQ<Impl>::completeStore(int store_idx)
 738 {
 739     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 740     assert(sq_hash_it != SQItHash.end());
 741     SQIt sq_it = (*sq_hash_it).second;
 742
 743     assert((*sq_it).inst);
 744     (*sq_it).completed = true;
 745     DynInstPtr inst = (*sq_it).inst;
 746
 747     --storesToWB;
 748
 749     if (isStalled() &&
 750         inst->seqNum == stallingStoreIsn) {
 751         DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 752                 "load [sn:%lli]\n",
 753                 stallingStoreIsn, (*stallingLoad)->seqNum);
 754         stalled = false;
 755         stallingStoreIsn = 0;
 756         be->replayMemInst((*stallingLoad));
 757     }
 758
 759     DPRINTF(OzoneLSQ, "Completing store idx:%i [sn:%lli], storesToWB:%i\n",
 760             inst->sqIdx, inst->seqNum, storesToWB);
 761
 762     assert(!storeQueue.empty());
 763     SQItHash.erase(sq_hash_it);
 764     SQIndices.push(inst->sqIdx);
 765     storeQueue.erase(sq_it);
 766     --stores;
 767
 768     inst->setCompleted();
 769     if (cpu->checker) {
 770         cpu->checker->tick(inst);
 771     }
 772 }
 773
 774 template <class Impl>
 775 void
 776 OzoneLWLSQ<Impl>::switchOut()
 777 {
 778     assert(storesToWB == 0);
 779     switchedOut = true;
 780     SQIt sq_it = --(storeQueue.end());
 781     while (storesToWB > 0 &&
 782            sq_it != storeQueue.end() &&
 783            (*sq_it).inst &&
 784            (*sq_it).canWB) {
 785
 786         DynInstPtr inst = (*sq_it).inst;
 787
 788         if ((*sq_it).size == 0 && !(*sq_it).completed) {
 789             sq_it--;
 790             continue;
 791         }
 792
 793         // Store conditionals don't complete until *after* they have written
 794         // back.  If it's here and not yet sent to memory, then don't bother
 795         // as it's not part of committed state.
 796         if (inst->isDataPrefetch() || (*sq_it).committed) {
 797             sq_it--;
 798             continue;
 799         } else if ((*sq_it).req->flags & LOCKED) {
 800             sq_it--;
 801             assert(!(*sq_it).canWB ||
 802                    ((*sq_it).canWB && (*sq_it).req->flags & LOCKED));
 803             continue;
 804         }
 805
 806         assert((*sq_it).req);
 807         assert(!(*sq_it).committed);
 808
 809         MemReqPtr req = (*sq_it).req;
 810         (*sq_it).committed = true;
 811
 812         req->cmd = Write;
 813         req->completionEvent = NULL;
 814         req->time = curTick;
 815         assert(!req->data);
 816         req->data = new uint8_t[64];
 817         memcpy(req->data, (uint8_t *)&(*sq_it).data, req->size);
 818
 819         DPRINTF(OzoneLSQ, "Switching out : Writing back store idx:%i PC:%#x "
 820                 "to Addr:%#x, data:%#x directly to memory [sn:%lli]\n",
 821                 inst->sqIdx,inst->readPC(),
 822                 req->paddr, *(req->data),
 823                 inst->seqNum);
 824
 825         switch((*sq_it).size) {
 826           case 1:
 827             cpu->write(req, (uint8_t &)(*sq_it).data);
 828             break;
 829           case 2:
 830             cpu->write(req, (uint16_t &)(*sq_it).data);
 831             break;
 832           case 4:
 833             cpu->write(req, (uint32_t &)(*sq_it).data);
 834             break;
 835           case 8:
 836             cpu->write(req, (uint64_t &)(*sq_it).data);
 837             break;
 838           default:
 839             panic("Unexpected store size!\n");
 840         }
 841     }
 842
 843     // Clear the queue to free up resources
 844     storeQueue.clear();
 845     loadQueue.clear();
 846     loads = stores = storesToWB = 0;
 847 }
 848
 849 template <class Impl>
 850 void
 851 OzoneLWLSQ<Impl>::takeOverFrom(ThreadContext *old_tc)
 852 {
 853     // Clear out any old state. May be redundant if this is the first time
 854     // the CPU is being used.
 855     stalled = false;
 856     isLoadBlocked = false;
 857     loadBlockedHandled = false;
 858     switchedOut = false;
 859
 860     // Could do simple checks here to see if indices are on twice
 861     while (!LQIndices.empty())
 862         LQIndices.pop();
 863     while (!SQIndices.empty())
 864         SQIndices.pop();
 865
 866     for (int i = 0; i < LQEntries * 2; i++) {
 867         LQIndices.push(i);
 868         SQIndices.push(i);
 869     }
 870
 871     usedPorts = 0;
 872
 873     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 874
 875     blockedLoadSeqNum = 0;
 876 }