src/cpu/ozone/lw_lsq_impl.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "config/use_checker.hh"
  32
  33 #include "arch/faults.hh"
  34 #include "base/str.hh"
  35 #include "cpu/ozone/lw_lsq.hh"
  36 #include "cpu/checker/cpu.hh"
  37
  38 template<class Impl>
  39 OzoneLWLSQ<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
  40                                                  OzoneLWLSQ *lsq_ptr)
  41     : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
  42 {
  43     this->setFlags(Event::AutoDelete);
  44 }
  45
  46 template<class Impl>
  47 void
  48 OzoneLWLSQ<Impl>::WritebackEvent::process()
  49 {
  50     if (!lsqPtr->isSwitchedOut()) {
  51         lsqPtr->writeback(inst, pkt);
  52     }
  53     delete pkt;
  54 }
  55
  56 template<class Impl>
  57 const char *
  58 OzoneLWLSQ<Impl>::WritebackEvent::description()
  59 {
  60     return "Store writeback event";
  61 }
  62
  63 template <class Impl>
  64 Tick
  65 OzoneLWLSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
  66 {
  67     panic("O3CPU model does not work with atomic mode!");
  68     return curTick;
  69 }
  70
  71 template <class Impl>
  72 void
  73 OzoneLWLSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
  74 {
  75     warn("O3CPU doesn't update things on a recvFunctional");
  76 }
  77
  78 template <class Impl>
  79 void
  80 OzoneLWLSQ<Impl>::DcachePort::recvStatusChange(Status status)
  81 {
  82     if (status == RangeChange)
  83         return;
  84
  85     panic("O3CPU doesn't expect recvStatusChange callback!");
  86 }
  87
  88 template <class Impl>
  89 bool
  90 OzoneLWLSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
  91 {
  92     lsq->completeDataAccess(pkt);
  93     return true;
  94 }
  95
  96 template <class Impl>
  97 void
  98 OzoneLWLSQ<Impl>::DcachePort::recvRetry()
  99 {
 100     lsq->recvRetry();
 101 }
 102
 103 template<class Impl>
 104 void
 105 OzoneLWLSQ<Impl>::completeDataAccess(PacketPtr pkt)
 106 {
 107     LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
 108     DynInstPtr inst = state->inst;
 109     DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
 110     DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
 111
 112     //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
 113
 114     if (isSwitchedOut() || inst->isSquashed()) {
 115         delete state;
 116         delete pkt;
 117         return;
 118     } else {
 119         if (!state->noWB) {
 120             writeback(inst, pkt);
 121         }
 122
 123         if (inst->isStore()) {
 124             completeStore(inst);
 125         }
 126     }
 127
 128     delete state;
 129     delete pkt;
 130 }
 131
 132 template <class Impl>
 133 OzoneLWLSQ<Impl>::OzoneLWLSQ()
 134     : switchedOut(false), dcachePort(this), loads(0), stores(0),
 135       storesToWB(0), storesInFlight(0), stalled(false), isStoreBlocked(false),
 136       isLoadBlocked(false), loadBlockedHandled(false)
 137 {
 138 }
 139
 140 template<class Impl>
 141 void
 142 OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
 143                        unsigned maxSQEntries, unsigned id)
 144 {
 145     DPRINTF(OzoneLSQ, "Creating OzoneLWLSQ%i object.\n",id);
 146
 147     lsqID = id;
 148
 149     LQEntries = maxLQEntries;
 150     SQEntries = maxSQEntries;
 151
 152     for (int i = 0; i < LQEntries * 2; i++) {
 153         LQIndices.push(i);
 154         SQIndices.push(i);
 155     }
 156
 157     mem = params->mem;
 158
 159     usedPorts = 0;
 160     cachePorts = params->cachePorts;
 161
 162     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 163
 164     blockedLoadSeqNum = 0;
 165 }
 166
 167 template<class Impl>
 168 std::string
 169 OzoneLWLSQ<Impl>::name() const
 170 {
 171     return "lsqunit";
 172 }
 173
 174 template<class Impl>
 175 void
 176 OzoneLWLSQ<Impl>::regStats()
 177 {
 178     lsqMemOrderViolation
 179         .name(name() + ".memOrderViolation")
 180         .desc("Number of memory ordering violations");
 181 }
 182
 183 template<class Impl>
 184 void
 185 OzoneLWLSQ<Impl>::setCPU(OzoneCPU *cpu_ptr)
 186 {
 187     cpu = cpu_ptr;
 188     dcachePort.setName(this->name() + "-dport");
 189
 190 #if USE_CHECKER
 191     if (cpu->checker) {
 192         cpu->checker->setDcachePort(&dcachePort);
 193     }
 194 #endif
 195 }
 196
 197 template<class Impl>
 198 void
 199 OzoneLWLSQ<Impl>::clearLQ()
 200 {
 201     loadQueue.clear();
 202 }
 203
 204 template<class Impl>
 205 void
 206 OzoneLWLSQ<Impl>::clearSQ()
 207 {
 208     storeQueue.clear();
 209 }
 210 /*
 211 template<class Impl>
 212 void
 213 OzoneLWLSQ<Impl>::setPageTable(PageTable *pt_ptr)
 214 {
 215     DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
 216     pTable = pt_ptr;
 217 }
 218 */
 219 template<class Impl>
 220 void
 221 OzoneLWLSQ<Impl>::resizeLQ(unsigned size)
 222 {
 223     assert( size >= LQEntries);
 224
 225     if (size > LQEntries) {
 226         while (size > loadQueue.size()) {
 227             DynInstPtr dummy;
 228             loadQueue.push_back(dummy);
 229             LQEntries++;
 230         }
 231     } else {
 232         LQEntries = size;
 233     }
 234
 235 }
 236
 237 template<class Impl>
 238 void
 239 OzoneLWLSQ<Impl>::resizeSQ(unsigned size)
 240 {
 241     if (size > SQEntries) {
 242         while (size > storeQueue.size()) {
 243             SQEntry dummy;
 244             storeQueue.push_back(dummy);
 245             SQEntries++;
 246         }
 247     } else {
 248         SQEntries = size;
 249     }
 250 }
 251
 252 template <class Impl>
 253 void
 254 OzoneLWLSQ<Impl>::insert(DynInstPtr &inst)
 255 {
 256     // Make sure we really have a memory reference.
 257     assert(inst->isMemRef());
 258
 259     // Make sure it's one of the two classes of memory references.
 260     assert(inst->isLoad() || inst->isStore());
 261
 262     if (inst->isLoad()) {
 263         insertLoad(inst);
 264     } else {
 265         insertStore(inst);
 266     }
 267 }
 268
 269 template <class Impl>
 270 void
 271 OzoneLWLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
 272 {
 273     assert(loads < LQEntries * 2);
 274     assert(!LQIndices.empty());
 275     int load_index = LQIndices.front();
 276     LQIndices.pop();
 277
 278     DPRINTF(OzoneLSQ, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
 279             load_inst->readPC(), load_index, load_inst->seqNum);
 280
 281     load_inst->lqIdx = load_index;
 282
 283     loadQueue.push_front(load_inst);
 284     LQItHash[load_index] = loadQueue.begin();
 285
 286     ++loads;
 287 }
 288
 289 template <class Impl>
 290 void
 291 OzoneLWLSQ<Impl>::insertStore(DynInstPtr &store_inst)
 292 {
 293     // Make sure it is not full before inserting an instruction.
 294     assert(stores - storesToWB < SQEntries);
 295
 296     assert(!SQIndices.empty());
 297     int store_index = SQIndices.front();
 298     SQIndices.pop();
 299
 300     DPRINTF(OzoneLSQ, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
 301             store_inst->readPC(), store_index, store_inst->seqNum);
 302
 303     store_inst->sqIdx = store_index;
 304     SQEntry entry(store_inst);
 305     if (loadQueue.empty()) {
 306         entry.lqIt = loadQueue.end();
 307     } else {
 308         entry.lqIt = loadQueue.begin();
 309     }
 310     storeQueue.push_front(entry);
 311
 312     SQItHash[store_index] = storeQueue.begin();
 313
 314     ++stores;
 315 }
 316
 317 template <class Impl>
 318 typename Impl::DynInstPtr
 319 OzoneLWLSQ<Impl>::getMemDepViolator()
 320 {
 321     DynInstPtr temp = memDepViolator;
 322
 323     memDepViolator = NULL;
 324
 325     return temp;
 326 }
 327
 328 template <class Impl>
 329 unsigned
 330 OzoneLWLSQ<Impl>::numFreeEntries()
 331 {
 332     unsigned free_lq_entries = LQEntries - loads;
 333     unsigned free_sq_entries = SQEntries - (stores + storesInFlight);
 334
 335     // Both the LQ and SQ entries have an extra dummy entry to differentiate
 336     // empty/full conditions.  Subtract 1 from the free entries.
 337     if (free_lq_entries < free_sq_entries) {
 338         return free_lq_entries - 1;
 339     } else {
 340         return free_sq_entries - 1;
 341     }
 342 }
 343
 344 template <class Impl>
 345 int
 346 OzoneLWLSQ<Impl>::numLoadsReady()
 347 {
 348     int retval = 0;
 349     LQIt lq_it = loadQueue.begin();
 350     LQIt end_it = loadQueue.end();
 351
 352     while (lq_it != end_it) {
 353         if ((*lq_it)->readyToIssue()) {
 354             ++retval;
 355         }
 356     }
 357
 358     return retval;
 359 }
 360
 361 template <class Impl>
 362 Fault
 363 OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst)
 364 {
 365     // Execute a specific load.
 366     Fault load_fault = NoFault;
 367
 368     DPRINTF(OzoneLSQ, "Executing load PC %#x, [sn:%lli]\n",
 369             inst->readPC(),inst->seqNum);
 370
 371     // Make sure it's really in the list.
 372     // Normally it should always be in the list.  However,
 373     /* due to a syscall it may not be the list.
 374 #ifdef DEBUG
 375     int i = loadHead;
 376     while (1) {
 377         if (i == loadTail && !find(inst)) {
 378             assert(0 && "Load not in the queue!");
 379         } else if (loadQueue[i] == inst) {
 380             break;
 381         }
 382
 383         i = i + 1;
 384         if (i >= LQEntries) {
 385             i = 0;
 386         }
 387     }
 388 #endif // DEBUG*/
 389
 390     load_fault = inst->initiateAcc();
 391
 392     // Might want to make sure that I'm not overwriting a previously faulting
 393     // instruction that hasn't been checked yet.
 394     // Actually probably want the oldest faulting load
 395     if (load_fault != NoFault) {
 396         DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum);
 397         if (!(inst->req->isUncacheable() && !inst->isAtCommit())) {
 398             inst->setExecuted();
 399         }
 400         // Maybe just set it as can commit here, although that might cause
 401         // some other problems with sending traps to the ROB too quickly.
 402         be->instToCommit(inst);
 403 //        iewStage->activityThisCycle();
 404     }
 405
 406     return load_fault;
 407 }
 408
 409 template <class Impl>
 410 Fault
 411 OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
 412 {
 413     // Make sure that a store exists.
 414     assert(stores != 0);
 415
 416     int store_idx = store_inst->sqIdx;
 417     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 418     assert(sq_hash_it != SQItHash.end());
 419     DPRINTF(OzoneLSQ, "Executing store PC %#x [sn:%lli]\n",
 420             store_inst->readPC(), store_inst->seqNum);
 421
 422     SQIt sq_it = (*sq_hash_it).second;
 423
 424     Fault store_fault = store_inst->initiateAcc();
 425
 426     // Store size should now be available.  Use it to get proper offset for
 427     // addr comparisons.
 428     int size = (*sq_it).size;
 429
 430     if (size == 0) {
 431         DPRINTF(OzoneLSQ,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
 432                 store_inst->readPC(),store_inst->seqNum);
 433
 434         return store_fault;
 435     }
 436
 437     assert(store_fault == NoFault);
 438
 439     if (!storeFaultInst) {
 440         if (store_fault != NoFault) {
 441             panic("Fault in a store instruction!");
 442             storeFaultInst = store_inst;
 443         } else if (store_inst->isStoreConditional()) {
 444             // Store conditionals need to set themselves as able to
 445             // writeback if we haven't had a fault by here.
 446             (*sq_it).canWB = true;
 447
 448             ++storesToWB;
 449             DPRINTF(OzoneLSQ, "Nonspeculative store! storesToWB:%i\n",
 450                     storesToWB);
 451         }
 452     }
 453
 454     LQIt lq_it = --(loadQueue.end());
 455
 456     if (!memDepViolator) {
 457         while (lq_it != loadQueue.end()) {
 458             if ((*lq_it)->seqNum < store_inst->seqNum) {
 459                 lq_it--;
 460                 continue;
 461             }
 462             // Actually should only check loads that have actually executed
 463             // Might be safe because effAddr is set to InvalAddr when the
 464             // dyn inst is created.
 465
 466             // Must actually check all addrs in the proper size range
 467             // Which is more correct than needs to be.  What if for now we just
 468             // assume all loads are quad-word loads, and do the addr based
 469             // on that.
 470             // @todo: Fix this, magic number being used here
 471             if (((*lq_it)->effAddr >> 8) ==
 472                 (store_inst->effAddr >> 8)) {
 473                 // A load incorrectly passed this store.  Squash and refetch.
 474                 // For now return a fault to show that it was unsuccessful.
 475                 memDepViolator = (*lq_it);
 476                 ++lsqMemOrderViolation;
 477
 478                 return TheISA::genMachineCheckFault();
 479             }
 480
 481             lq_it--;
 482         }
 483
 484         // If we've reached this point, there was no violation.
 485         memDepViolator = NULL;
 486     }
 487
 488     return store_fault;
 489 }
 490
 491 template <class Impl>
 492 void
 493 OzoneLWLSQ<Impl>::commitLoad()
 494 {
 495     assert(!loadQueue.empty());
 496
 497     DPRINTF(OzoneLSQ, "[sn:%lli] Committing head load instruction, PC %#x\n",
 498             loadQueue.back()->seqNum, loadQueue.back()->readPC());
 499
 500     LQIndices.push(loadQueue.back()->lqIdx);
 501     LQItHash.erase(loadQueue.back()->lqIdx);
 502
 503     loadQueue.pop_back();
 504
 505     --loads;
 506 }
 507
 508 template <class Impl>
 509 void
 510 OzoneLWLSQ<Impl>::commitLoads(InstSeqNum &youngest_inst)
 511 {
 512     assert(loads == 0 || !loadQueue.empty());
 513
 514     while (loads != 0 &&
 515            loadQueue.back()->seqNum <= youngest_inst) {
 516         commitLoad();
 517     }
 518 }
 519
 520 template <class Impl>
 521 void
 522 OzoneLWLSQ<Impl>::commitStores(InstSeqNum &youngest_inst)
 523 {
 524     assert(stores == 0 || !storeQueue.empty());
 525
 526     SQIt sq_it = --(storeQueue.end());
 527     while (!storeQueue.empty() && sq_it != storeQueue.end()) {
 528         assert((*sq_it).inst);
 529         if (!(*sq_it).canWB) {
 530             if ((*sq_it).inst->seqNum > youngest_inst) {
 531                 break;
 532             }
 533             ++storesToWB;
 534
 535             DPRINTF(OzoneLSQ, "Marking store as able to write back, PC "
 536                     "%#x [sn:%lli], storesToWB:%i\n",
 537                     (*sq_it).inst->readPC(),
 538                     (*sq_it).inst->seqNum,
 539                     storesToWB);
 540
 541             (*sq_it).canWB = true;
 542         }
 543
 544         sq_it--;
 545     }
 546 }
 547
 548 template <class Impl>
 549 void
 550 OzoneLWLSQ<Impl>::writebackStores()
 551 {
 552     SQIt sq_it = --(storeQueue.end());
 553     while (storesToWB > 0 &&
 554            sq_it != storeQueue.end() &&
 555            (*sq_it).inst &&
 556            (*sq_it).canWB &&
 557            usedPorts < cachePorts) {
 558
 559         if (isStoreBlocked) {
 560             DPRINTF(OzoneLSQ, "Unable to write back any more stores, cache"
 561                     " is blocked!\n");
 562             break;
 563         }
 564
 565         DynInstPtr inst = (*sq_it).inst;
 566
 567         if ((*sq_it).size == 0 && !(*sq_it).completed) {
 568             sq_it--;
 569             removeStore(inst->sqIdx);
 570             completeStore(inst);
 571             continue;
 572         }
 573
 574         if (inst->isDataPrefetch() || (*sq_it).committed) {
 575             sq_it--;
 576             continue;
 577         }
 578
 579         ++usedPorts;
 580
 581         assert((*sq_it).req);
 582         assert(!(*sq_it).committed);
 583
 584         Request *req = (*sq_it).req;
 585         (*sq_it).committed = true;
 586
 587         assert(!inst->memData);
 588         inst->memData = new uint8_t[64];
 589         memcpy(inst->memData, (uint8_t *)&(*sq_it).data,
 590                req->getSize());
 591
 592         PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
 593         data_pkt->dataStatic(inst->memData);
 594
 595         LSQSenderState *state = new LSQSenderState;
 596         state->isLoad = false;
 597         state->idx = inst->sqIdx;
 598         state->inst = inst;
 599         data_pkt->senderState = state;
 600
 601         DPRINTF(OzoneLSQ, "D-Cache: Writing back store PC:%#x "
 602                 "to Addr:%#x, data:%#x [sn:%lli]\n",
 603                 (*sq_it).inst->readPC(),
 604                 req->getPaddr(), *(inst->memData),
 605                 inst->seqNum);
 606
 607         // @todo: Remove this SC hack once the memory system handles it.
 608         if (req->isLocked()) {
 609             if (req->isUncacheable()) {
 610                 req->setScResult(2);
 611             } else {
 612                 if (cpu->lockFlag) {
 613                     req->setScResult(1);
 614                 } else {
 615                     req->setScResult(0);
 616                     // Hack: Instantly complete this store.
 617                     completeDataAccess(data_pkt);
 618                     --sq_it;
 619                     continue;
 620                 }
 621             }
 622         } else {
 623             // Non-store conditionals do not need a writeback.
 624             state->noWB = true;
 625         }
 626
 627         if (!dcachePort.sendTiming(data_pkt)) {
 628             // Need to handle becoming blocked on a store.
 629             isStoreBlocked = true;
 630             assert(retryPkt == NULL);
 631             retryPkt = data_pkt;
 632         } else {
 633             storePostSend(data_pkt, inst);
 634             --sq_it;
 635         }
 636 /*
 637         DPRINTF(OzoneLSQ, "D-Cache: Writing back store idx:%i PC:%#x "
 638                 "to Addr:%#x, data:%#x [sn:%lli]\n",
 639                 inst->sqIdx,inst->readPC(),
 640                 req->paddr, *(req->data),
 641                 inst->seqNum);
 642         DPRINTF(OzoneLSQ, "StoresInFlight: %i\n",
 643                 storesInFlight + 1);
 644
 645         if (dcacheInterface) {
 646             assert(!req->completionEvent);
 647             StoreCompletionEvent *store_event = new
 648                 StoreCompletionEvent(inst, be, NULL, this);
 649             req->completionEvent = store_event;
 650
 651             MemAccessResult result = dcacheInterface->access(req);
 652
 653             if (isStalled() &&
 654                 inst->seqNum == stallingStoreIsn) {
 655                 DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 656                         "load [sn:%lli]\n",
 657                         stallingStoreIsn, (*stallingLoad)->seqNum);
 658                 stalled = false;
 659                 stallingStoreIsn = 0;
 660                 be->replayMemInst((*stallingLoad));
 661             }
 662
 663             if (result != MA_HIT && dcacheInterface->doEvents()) {
 664                 store_event->miss = true;
 665                 typename BackEnd::LdWritebackEvent *wb = NULL;
 666                 if (req->isLocked()) {
 667                     wb = new typename BackEnd::LdWritebackEvent(inst,
 668                                                             be);
 669                     store_event->wbEvent = wb;
 670                 }
 671
 672                 DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
 673
 674 //                DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
 675 //                        inst->seqNum);
 676
 677                 be->addDcacheMiss(inst);
 678
 679                 lastDcacheStall = curTick;
 680
 681                 _status = DcacheMissStall;
 682
 683                 // Increment stat here or something
 684
 685                 sq_it--;
 686             } else {
 687                 DPRINTF(OzoneLSQ,"D-Cache: Write Hit on idx:%i !\n",
 688                         inst->sqIdx);
 689
 690 //                DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 691 //                        inst->seqNum);
 692
 693                 if (req->isLocked()) {
 694                     // Stx_C does not generate a system port
 695                     // transaction in the 21264, but that might be
 696                     // hard to accomplish in this model.
 697
 698                     typename BackEnd::LdWritebackEvent *wb =
 699                         new typename BackEnd::LdWritebackEvent(inst,
 700                                                                be);
 701                     store_event->wbEvent = wb;
 702                 }
 703                 sq_it--;
 704             }
 705             ++storesInFlight;
 706 //            removeStore(inst->sqIdx);
 707         } else {
 708             panic("Must HAVE DCACHE!!!!!\n");
 709         }
 710 */
 711     }
 712
 713     // Not sure this should set it to 0.
 714     usedPorts = 0;
 715
 716     assert(stores >= 0 && storesToWB >= 0);
 717 }
 718
 719 template <class Impl>
 720 void
 721 OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
 722 {
 723     DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
 724             "(Loads:%i Stores:%i)\n",squashed_num,loads,stores+storesInFlight);
 725
 726
 727     LQIt lq_it = loadQueue.begin();
 728
 729     while (loads != 0 && (*lq_it)->seqNum > squashed_num) {
 730         assert(!loadQueue.empty());
 731         // Clear the smart pointer to make sure it is decremented.
 732         DPRINTF(OzoneLSQ,"Load Instruction PC %#x squashed, "
 733                 "[sn:%lli]\n",
 734                 (*lq_it)->readPC(),
 735                 (*lq_it)->seqNum);
 736
 737         if (isStalled() && lq_it == stallingLoad) {
 738             stalled = false;
 739             stallingStoreIsn = 0;
 740             stallingLoad = NULL;
 741         }
 742
 743         --loads;
 744
 745         // Inefficient!
 746         LQHashIt lq_hash_it = LQItHash.find((*lq_it)->lqIdx);
 747         assert(lq_hash_it != LQItHash.end());
 748         LQItHash.erase(lq_hash_it);
 749         LQIndices.push((*lq_it)->lqIdx);
 750         loadQueue.erase(lq_it++);
 751     }
 752
 753     if (isLoadBlocked) {
 754         if (squashed_num < blockedLoadSeqNum) {
 755             isLoadBlocked = false;
 756             loadBlockedHandled = false;
 757             blockedLoadSeqNum = 0;
 758         }
 759     }
 760
 761     SQIt sq_it = storeQueue.begin();
 762
 763     while (stores != 0 && (*sq_it).inst->seqNum > squashed_num) {
 764         assert(!storeQueue.empty());
 765
 766         if ((*sq_it).canWB) {
 767             break;
 768         }
 769
 770         // Clear the smart pointer to make sure it is decremented.
 771         DPRINTF(OzoneLSQ,"Store Instruction PC %#x idx:%i squashed [sn:%lli]\n",
 772                 (*sq_it).inst->readPC(), (*sq_it).inst->sqIdx,
 773                 (*sq_it).inst->seqNum);
 774
 775         // I don't think this can happen.  It should have been cleared by the
 776         // stalling load.
 777         if (isStalled() &&
 778             (*sq_it).inst->seqNum == stallingStoreIsn) {
 779             panic("Is stalled should have been cleared by stalling load!\n");
 780             stalled = false;
 781             stallingStoreIsn = 0;
 782         }
 783
 784         SQHashIt sq_hash_it = SQItHash.find((*sq_it).inst->sqIdx);
 785         assert(sq_hash_it != SQItHash.end());
 786         SQItHash.erase(sq_hash_it);
 787         SQIndices.push((*sq_it).inst->sqIdx);
 788         (*sq_it).inst = NULL;
 789         (*sq_it).canWB = 0;
 790         (*sq_it).req = NULL;
 791         --stores;
 792         storeQueue.erase(sq_it++);
 793     }
 794 }
 795
 796 template <class Impl>
 797 void
 798 OzoneLWLSQ<Impl>::dumpInsts()
 799 {
 800     cprintf("Load store queue: Dumping instructions.\n");
 801     cprintf("Load queue size: %i\n", loads);
 802     cprintf("Load queue: ");
 803
 804     LQIt lq_it = --(loadQueue.end());
 805
 806     while (lq_it != loadQueue.end() && (*lq_it)) {
 807         cprintf("[sn:%lli] %#x ", (*lq_it)->seqNum,
 808                 (*lq_it)->readPC());
 809
 810         lq_it--;
 811     }
 812
 813     cprintf("\nStore queue size: %i\n", stores);
 814     cprintf("Store queue: ");
 815
 816     SQIt sq_it = --(storeQueue.end());
 817
 818     while (sq_it != storeQueue.end() && (*sq_it).inst) {
 819         cprintf("[sn:%lli]\nPC:%#x\nSize:%i\nCommitted:%i\nCompleted:%i\ncanWB:%i\n",
 820                 (*sq_it).inst->seqNum,
 821                 (*sq_it).inst->readPC(),
 822                 (*sq_it).size,
 823                 (*sq_it).committed,
 824                 (*sq_it).completed,
 825                 (*sq_it).canWB);
 826
 827         sq_it--;
 828     }
 829
 830     cprintf("\n");
 831 }
 832
 833 template <class Impl>
 834 void
 835 OzoneLWLSQ<Impl>::storePostSend(Packet *pkt, DynInstPtr &inst)
 836 {
 837     if (isStalled() &&
 838         inst->seqNum == stallingStoreIsn) {
 839         DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 840                 "load [sn:%lli]\n",
 841                 stallingStoreIsn, (*stallingLoad)->seqNum);
 842         stalled = false;
 843         stallingStoreIsn = 0;
 844         be->replayMemInst((*stallingLoad));
 845     }
 846
 847     if (!inst->isStoreConditional()) {
 848         // The store is basically completed at this time. This
 849         // only works so long as the checker doesn't try to
 850         // verify the value in memory for stores.
 851         inst->setCompleted();
 852 #if USE_CHECKER
 853         if (cpu->checker) {
 854             cpu->checker->verify(inst);
 855         }
 856 #endif
 857     }
 858
 859     if (pkt->result != Packet::Success) {
 860         DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
 861
 862         DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
 863                 inst->seqNum);
 864
 865         //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
 866
 867         //DPRINTF(OzoneLWLSQ, "Added MSHR. count = %i\n",mshrSeqNums.size());
 868
 869         // @todo: Increment stat here.
 870     } else {
 871         DPRINTF(OzoneLSQ,"D-Cache: Write Hit!\n");
 872
 873         DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 874                 inst->seqNum);
 875     }
 876 }
 877
 878 template <class Impl>
 879 void
 880 OzoneLWLSQ<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
 881 {
 882     // Squashed instructions do not need to complete their access.
 883     if (inst->isSquashed()) {
 884         assert(!inst->isStore());
 885         return;
 886     }
 887
 888     if (!inst->isExecuted()) {
 889         inst->setExecuted();
 890
 891         // Complete access to copy data to proper place.
 892         inst->completeAcc(pkt);
 893     }
 894
 895     // Need to insert instruction into queue to commit
 896     be->instToCommit(inst);
 897 }
 898
 899 template <class Impl>
 900 void
 901 OzoneLWLSQ<Impl>::removeStore(int store_idx)
 902 {
 903     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 904     assert(sq_hash_it != SQItHash.end());
 905     SQIt sq_it = (*sq_hash_it).second;
 906
 907     assert((*sq_it).inst);
 908     (*sq_it).completed = true;
 909     DynInstPtr inst = (*sq_it).inst;
 910
 911     if (isStalled() &&
 912         inst->seqNum == stallingStoreIsn) {
 913         DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 914                 "load [sn:%lli]\n",
 915                 stallingStoreIsn, (*stallingLoad)->seqNum);
 916         stalled = false;
 917         stallingStoreIsn = 0;
 918         be->replayMemInst((*stallingLoad));
 919     }
 920
 921     DPRINTF(OzoneLSQ, "Completing store idx:%i [sn:%lli], storesToWB:%i\n",
 922             inst->sqIdx, inst->seqNum, storesToWB);
 923
 924     assert(!storeQueue.empty());
 925     SQItHash.erase(sq_hash_it);
 926     SQIndices.push(inst->sqIdx);
 927     storeQueue.erase(sq_it);
 928 }
 929
 930 template <class Impl>
 931 void
 932 OzoneLWLSQ<Impl>::completeStore(DynInstPtr &inst)
 933 {
 934     --storesToWB;
 935     --stores;
 936
 937     inst->setCompleted();
 938 #if USE_CHECKER
 939     if (cpu->checker) {
 940         cpu->checker->verify(inst);
 941     }
 942 #endif
 943 }
 944
 945 template <class Impl>
 946 void
 947 OzoneLWLSQ<Impl>::recvRetry()
 948 {
 949     panic("Unimplemented!");
 950 }
 951
 952 template <class Impl>
 953 void
 954 OzoneLWLSQ<Impl>::switchOut()
 955 {
 956     assert(storesToWB == 0);
 957     switchedOut = true;
 958
 959     // Clear the queue to free up resources
 960     assert(stores == 0);
 961     assert(storeQueue.empty());
 962     assert(loads == 0);
 963     assert(loadQueue.empty());
 964     assert(storesInFlight == 0);
 965     storeQueue.clear();
 966     loadQueue.clear();
 967     loads = stores = storesToWB = storesInFlight = 0;
 968 }
 969
 970 template <class Impl>
 971 void
 972 OzoneLWLSQ<Impl>::takeOverFrom(ThreadContext *old_tc)
 973 {
 974     // Clear out any old state. May be redundant if this is the first time
 975     // the CPU is being used.
 976     stalled = false;
 977     isLoadBlocked = false;
 978     loadBlockedHandled = false;
 979     switchedOut = false;
 980
 981     // Could do simple checks here to see if indices are on twice
 982     while (!LQIndices.empty())
 983         LQIndices.pop();
 984     while (!SQIndices.empty())
 985         SQIndices.pop();
 986
 987     for (int i = 0; i < LQEntries * 2; i++) {
 988         LQIndices.push(i);
 989         SQIndices.push(i);
 990     }
 991
 992     usedPorts = 0;
 993
 994     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 995
 996     blockedLoadSeqNum = 0;
 997 }