src/cpu/ozone/lw_lsq_impl.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "config/use_checker.hh"
  32
  33 #include "arch/isa_traits.hh"
  34 #include "base/str.hh"
  35 #include "cpu/ozone/lw_lsq.hh"
  36 #include "cpu/checker/cpu.hh"
  37
  38 template<class Impl>
  39 OzoneLWLSQ<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
  40                                                  OzoneLWLSQ *lsq_ptr)
  41     : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
  42 {
  43     this->setFlags(Event::AutoDelete);
  44 }
  45
  46 template<class Impl>
  47 void
  48 OzoneLWLSQ<Impl>::WritebackEvent::process()
  49 {
  50     if (!lsqPtr->isSwitchedOut()) {
  51         lsqPtr->writeback(inst, pkt);
  52     }
  53     delete pkt;
  54 }
  55
  56 template<class Impl>
  57 const char *
  58 OzoneLWLSQ<Impl>::WritebackEvent::description()
  59 {
  60     return "Store writeback event";
  61 }
  62
  63 template <class Impl>
  64 Tick
  65 OzoneLWLSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
  66 {
  67     panic("O3CPU model does not work with atomic mode!");
  68     return curTick;
  69 }
  70
  71 template <class Impl>
  72 void
  73 OzoneLWLSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
  74 {
  75     panic("O3CPU doesn't expect recvFunctional callback!");
  76 }
  77
  78 template <class Impl>
  79 void
  80 OzoneLWLSQ<Impl>::DcachePort::recvStatusChange(Status status)
  81 {
  82     if (status == RangeChange)
  83         return;
  84
  85     panic("O3CPU doesn't expect recvStatusChange callback!");
  86 }
  87
  88 template <class Impl>
  89 bool
  90 OzoneLWLSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
  91 {
  92     lsq->completeDataAccess(pkt);
  93     return true;
  94 }
  95
  96 template <class Impl>
  97 void
  98 OzoneLWLSQ<Impl>::DcachePort::recvRetry()
  99 {
 100     lsq->recvRetry();
 101 }
 102
 103 template<class Impl>
 104 void
 105 OzoneLWLSQ<Impl>::completeDataAccess(PacketPtr pkt)
 106 {
 107     LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
 108     DynInstPtr inst = state->inst;
 109     DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
 110     DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
 111
 112     //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
 113
 114     if (isSwitchedOut() || inst->isSquashed()) {
 115         delete state;
 116         delete pkt;
 117         return;
 118     } else {
 119         if (!state->noWB) {
 120             writeback(inst, pkt);
 121         }
 122
 123         if (inst->isStore()) {
 124             completeStore(state->idx);
 125         }
 126     }
 127
 128     delete state;
 129     delete pkt;
 130 }
 131
 132 template <class Impl>
 133 OzoneLWLSQ<Impl>::OzoneLWLSQ()
 134     : switchedOut(false), loads(0), stores(0), storesToWB(0), stalled(false),
 135       isStoreBlocked(false), isLoadBlocked(false), loadBlockedHandled(false)
 136 {
 137 }
 138
 139 template<class Impl>
 140 void
 141 OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
 142                        unsigned maxSQEntries, unsigned id)
 143 {
 144     DPRINTF(OzoneLSQ, "Creating OzoneLWLSQ%i object.\n",id);
 145
 146     lsqID = id;
 147
 148     LQEntries = maxLQEntries;
 149     SQEntries = maxSQEntries;
 150
 151     for (int i = 0; i < LQEntries * 2; i++) {
 152         LQIndices.push(i);
 153         SQIndices.push(i);
 154     }
 155
 156     mem = params->mem;
 157
 158     usedPorts = 0;
 159     cachePorts = params->cachePorts;
 160
 161     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 162
 163     blockedLoadSeqNum = 0;
 164 }
 165
 166 template<class Impl>
 167 std::string
 168 OzoneLWLSQ<Impl>::name() const
 169 {
 170     return "lsqunit";
 171 }
 172
 173 template<class Impl>
 174 void
 175 OzoneLWLSQ<Impl>::setCPU(OzoneCPU *cpu_ptr)
 176 {
 177     cpu = cpu_ptr;
 178     dcachePort = new DcachePort(cpu, this);
 179
 180     Port *mem_dport = mem->getPort("");
 181     dcachePort->setPeer(mem_dport);
 182     mem_dport->setPeer(dcachePort);
 183
 184 #if USE_CHECKER
 185     if (cpu->checker) {
 186         cpu->checker->setDcachePort(dcachePort);
 187     }
 188 #endif
 189 }
 190
 191 template<class Impl>
 192 void
 193 OzoneLWLSQ<Impl>::clearLQ()
 194 {
 195     loadQueue.clear();
 196 }
 197
 198 template<class Impl>
 199 void
 200 OzoneLWLSQ<Impl>::clearSQ()
 201 {
 202     storeQueue.clear();
 203 }
 204 /*
 205 template<class Impl>
 206 void
 207 OzoneLWLSQ<Impl>::setPageTable(PageTable *pt_ptr)
 208 {
 209     DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
 210     pTable = pt_ptr;
 211 }
 212 */
 213 template<class Impl>
 214 void
 215 OzoneLWLSQ<Impl>::resizeLQ(unsigned size)
 216 {
 217     assert( size >= LQEntries);
 218
 219     if (size > LQEntries) {
 220         while (size > loadQueue.size()) {
 221             DynInstPtr dummy;
 222             loadQueue.push_back(dummy);
 223             LQEntries++;
 224         }
 225     } else {
 226         LQEntries = size;
 227     }
 228
 229 }
 230
 231 template<class Impl>
 232 void
 233 OzoneLWLSQ<Impl>::resizeSQ(unsigned size)
 234 {
 235     if (size > SQEntries) {
 236         while (size > storeQueue.size()) {
 237             SQEntry dummy;
 238             storeQueue.push_back(dummy);
 239             SQEntries++;
 240         }
 241     } else {
 242         SQEntries = size;
 243     }
 244 }
 245
 246 template <class Impl>
 247 void
 248 OzoneLWLSQ<Impl>::insert(DynInstPtr &inst)
 249 {
 250     // Make sure we really have a memory reference.
 251     assert(inst->isMemRef());
 252
 253     // Make sure it's one of the two classes of memory references.
 254     assert(inst->isLoad() || inst->isStore());
 255
 256     if (inst->isLoad()) {
 257         insertLoad(inst);
 258     } else {
 259         insertStore(inst);
 260     }
 261 }
 262
 263 template <class Impl>
 264 void
 265 OzoneLWLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
 266 {
 267     assert(loads < LQEntries * 2);
 268     assert(!LQIndices.empty());
 269     int load_index = LQIndices.front();
 270     LQIndices.pop();
 271
 272     DPRINTF(OzoneLSQ, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
 273             load_inst->readPC(), load_index, load_inst->seqNum);
 274
 275     load_inst->lqIdx = load_index;
 276
 277     loadQueue.push_front(load_inst);
 278     LQItHash[load_index] = loadQueue.begin();
 279
 280     ++loads;
 281 }
 282
 283 template <class Impl>
 284 void
 285 OzoneLWLSQ<Impl>::insertStore(DynInstPtr &store_inst)
 286 {
 287     // Make sure it is not full before inserting an instruction.
 288     assert(stores - storesToWB < SQEntries);
 289
 290     assert(!SQIndices.empty());
 291     int store_index = SQIndices.front();
 292     SQIndices.pop();
 293
 294     DPRINTF(OzoneLSQ, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
 295             store_inst->readPC(), store_index, store_inst->seqNum);
 296
 297     store_inst->sqIdx = store_index;
 298     SQEntry entry(store_inst);
 299     if (loadQueue.empty()) {
 300         entry.lqIt = loadQueue.end();
 301     } else {
 302         entry.lqIt = loadQueue.begin();
 303     }
 304     storeQueue.push_front(entry);
 305
 306     SQItHash[store_index] = storeQueue.begin();
 307
 308     ++stores;
 309 }
 310
 311 template <class Impl>
 312 typename Impl::DynInstPtr
 313 OzoneLWLSQ<Impl>::getMemDepViolator()
 314 {
 315     DynInstPtr temp = memDepViolator;
 316
 317     memDepViolator = NULL;
 318
 319     return temp;
 320 }
 321
 322 template <class Impl>
 323 unsigned
 324 OzoneLWLSQ<Impl>::numFreeEntries()
 325 {
 326     unsigned free_lq_entries = LQEntries - loads;
 327     unsigned free_sq_entries = SQEntries - stores;
 328
 329     // Both the LQ and SQ entries have an extra dummy entry to differentiate
 330     // empty/full conditions.  Subtract 1 from the free entries.
 331     if (free_lq_entries < free_sq_entries) {
 332         return free_lq_entries - 1;
 333     } else {
 334         return free_sq_entries - 1;
 335     }
 336 }
 337
 338 template <class Impl>
 339 int
 340 OzoneLWLSQ<Impl>::numLoadsReady()
 341 {
 342     int retval = 0;
 343     LQIt lq_it = loadQueue.begin();
 344     LQIt end_it = loadQueue.end();
 345
 346     while (lq_it != end_it) {
 347         if ((*lq_it)->readyToIssue()) {
 348             ++retval;
 349         }
 350     }
 351
 352     return retval;
 353 }
 354
 355 template <class Impl>
 356 Fault
 357 OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst)
 358 {
 359     // Execute a specific load.
 360     Fault load_fault = NoFault;
 361
 362     DPRINTF(OzoneLSQ, "Executing load PC %#x, [sn:%lli]\n",
 363             inst->readPC(),inst->seqNum);
 364
 365     // Make sure it's really in the list.
 366     // Normally it should always be in the list.  However,
 367     /* due to a syscall it may not be the list.
 368 #ifdef DEBUG
 369     int i = loadHead;
 370     while (1) {
 371         if (i == loadTail && !find(inst)) {
 372             assert(0 && "Load not in the queue!");
 373         } else if (loadQueue[i] == inst) {
 374             break;
 375         }
 376
 377         i = i + 1;
 378         if (i >= LQEntries) {
 379             i = 0;
 380         }
 381     }
 382 #endif // DEBUG*/
 383
 384     load_fault = inst->initiateAcc();
 385
 386     // Might want to make sure that I'm not overwriting a previously faulting
 387     // instruction that hasn't been checked yet.
 388     // Actually probably want the oldest faulting load
 389     if (load_fault != NoFault) {
 390         DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum);
 391         // Maybe just set it as can commit here, although that might cause
 392         // some other problems with sending traps to the ROB too quickly.
 393         be->instToCommit(inst);
 394 //        iewStage->activityThisCycle();
 395     }
 396
 397     return load_fault;
 398 }
 399
 400 template <class Impl>
 401 Fault
 402 OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
 403 {
 404     // Make sure that a store exists.
 405     assert(stores != 0);
 406
 407     int store_idx = store_inst->sqIdx;
 408     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 409     assert(sq_hash_it != SQItHash.end());
 410     DPRINTF(OzoneLSQ, "Executing store PC %#x [sn:%lli]\n",
 411             store_inst->readPC(), store_inst->seqNum);
 412
 413     SQIt sq_it = (*sq_hash_it).second;
 414
 415     Fault store_fault = store_inst->initiateAcc();
 416
 417     // Store size should now be available.  Use it to get proper offset for
 418     // addr comparisons.
 419     int size = (*sq_it).size;
 420
 421     if (size == 0) {
 422         DPRINTF(OzoneLSQ,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
 423                 store_inst->readPC(),store_inst->seqNum);
 424
 425         return store_fault;
 426     }
 427
 428     assert(store_fault == NoFault);
 429
 430     if (!storeFaultInst) {
 431         if (store_fault != NoFault) {
 432             panic("Fault in a store instruction!");
 433             storeFaultInst = store_inst;
 434         } else if (store_inst->isStoreConditional()) {
 435             // Store conditionals need to set themselves as able to
 436             // writeback if we haven't had a fault by here.
 437             (*sq_it).canWB = true;
 438
 439             ++storesToWB;
 440             DPRINTF(OzoneLSQ, "Nonspeculative store! storesToWB:%i\n",
 441                     storesToWB);
 442         }
 443     }
 444
 445     LQIt lq_it = --(loadQueue.end());
 446
 447     if (!memDepViolator) {
 448         while (lq_it != loadQueue.end()) {
 449             if ((*lq_it)->seqNum < store_inst->seqNum) {
 450                 lq_it--;
 451                 continue;
 452             }
 453             // Actually should only check loads that have actually executed
 454             // Might be safe because effAddr is set to InvalAddr when the
 455             // dyn inst is created.
 456
 457             // Must actually check all addrs in the proper size range
 458             // Which is more correct than needs to be.  What if for now we just
 459             // assume all loads are quad-word loads, and do the addr based
 460             // on that.
 461             // @todo: Fix this, magic number being used here
 462             if (((*lq_it)->effAddr >> 8) ==
 463                 (store_inst->effAddr >> 8)) {
 464                 // A load incorrectly passed this store.  Squash and refetch.
 465                 // For now return a fault to show that it was unsuccessful.
 466                 memDepViolator = (*lq_it);
 467
 468                 return TheISA::genMachineCheckFault();
 469             }
 470
 471             lq_it--;
 472         }
 473
 474         // If we've reached this point, there was no violation.
 475         memDepViolator = NULL;
 476     }
 477
 478     return store_fault;
 479 }
 480
 481 template <class Impl>
 482 void
 483 OzoneLWLSQ<Impl>::commitLoad()
 484 {
 485     assert(!loadQueue.empty());
 486
 487     DPRINTF(OzoneLSQ, "[sn:%lli] Committing head load instruction, PC %#x\n",
 488             loadQueue.back()->seqNum, loadQueue.back()->readPC());
 489
 490     LQIndices.push(loadQueue.back()->lqIdx);
 491     LQItHash.erase(loadQueue.back()->lqIdx);
 492
 493     loadQueue.pop_back();
 494
 495     --loads;
 496 }
 497
 498 template <class Impl>
 499 void
 500 OzoneLWLSQ<Impl>::commitLoads(InstSeqNum &youngest_inst)
 501 {
 502     assert(loads == 0 || !loadQueue.empty());
 503
 504     while (loads != 0 &&
 505            loadQueue.back()->seqNum <= youngest_inst) {
 506         commitLoad();
 507     }
 508 }
 509
 510 template <class Impl>
 511 void
 512 OzoneLWLSQ<Impl>::commitStores(InstSeqNum &youngest_inst)
 513 {
 514     assert(stores == 0 || !storeQueue.empty());
 515
 516     SQIt sq_it = --(storeQueue.end());
 517     while (!storeQueue.empty() && sq_it != storeQueue.end()) {
 518         assert((*sq_it).inst);
 519         if (!(*sq_it).canWB) {
 520             if ((*sq_it).inst->seqNum > youngest_inst) {
 521                 break;
 522             }
 523             ++storesToWB;
 524
 525             DPRINTF(OzoneLSQ, "Marking store as able to write back, PC "
 526                     "%#x [sn:%lli], storesToWB:%i\n",
 527                     (*sq_it).inst->readPC(),
 528                     (*sq_it).inst->seqNum,
 529                     storesToWB);
 530
 531             (*sq_it).canWB = true;
 532         }
 533
 534         sq_it--;
 535     }
 536 }
 537
 538 template <class Impl>
 539 void
 540 OzoneLWLSQ<Impl>::writebackStores()
 541 {
 542     SQIt sq_it = --(storeQueue.end());
 543     while (storesToWB > 0 &&
 544            sq_it != storeQueue.end() &&
 545            (*sq_it).inst &&
 546            (*sq_it).canWB &&
 547            usedPorts < cachePorts) {
 548
 549         if (isStoreBlocked) {
 550             DPRINTF(OzoneLSQ, "Unable to write back any more stores, cache"
 551                     " is blocked!\n");
 552             break;
 553         }
 554
 555         DynInstPtr inst = (*sq_it).inst;
 556
 557         if ((*sq_it).size == 0 && !(*sq_it).completed) {
 558             sq_it--;
 559             completeStore(inst->sqIdx);
 560
 561             continue;
 562         }
 563
 564         if (inst->isDataPrefetch() || (*sq_it).committed) {
 565             sq_it--;
 566             continue;
 567         }
 568
 569         ++usedPorts;
 570
 571         assert((*sq_it).req);
 572         assert(!(*sq_it).committed);
 573
 574         Request *req = (*sq_it).req;
 575         (*sq_it).committed = true;
 576
 577         assert(!inst->memData);
 578         inst->memData = new uint8_t[64];
 579         memcpy(inst->memData, (uint8_t *)&(*sq_it).data,
 580                req->getSize());
 581
 582         PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
 583         data_pkt->dataStatic(inst->memData);
 584
 585         LSQSenderState *state = new LSQSenderState;
 586         state->isLoad = false;
 587         state->idx = inst->sqIdx;
 588         state->inst = inst;
 589         data_pkt->senderState = state;
 590
 591         DPRINTF(OzoneLSQ, "D-Cache: Writing back store PC:%#x "
 592                 "to Addr:%#x, data:%#x [sn:%lli]\n",
 593                 (*sq_it).inst->readPC(),
 594                 req->getPaddr(), *(inst->memData),
 595                 inst->seqNum);
 596
 597         // @todo: Remove this SC hack once the memory system handles it.
 598         if (req->getFlags() & LOCKED) {
 599             if (req->getFlags() & UNCACHEABLE) {
 600                 req->setScResult(2);
 601             } else {
 602                 if (cpu->lockFlag) {
 603                     req->setScResult(1);
 604                 } else {
 605                     req->setScResult(0);
 606                     // Hack: Instantly complete this store.
 607                     completeDataAccess(data_pkt);
 608                     --sq_it;
 609                     continue;
 610                 }
 611             }
 612         } else {
 613             // Non-store conditionals do not need a writeback.
 614             state->noWB = true;
 615         }
 616
 617         if (!dcachePort->sendTiming(data_pkt)) {
 618             // Need to handle becoming blocked on a store.
 619             isStoreBlocked = true;
 620             assert(retryPkt == NULL);
 621             retryPkt = data_pkt;
 622         } else {
 623             storePostSend(data_pkt, inst);
 624             --sq_it;
 625         }
 626 /*
 627         DPRINTF(OzoneLSQ, "D-Cache: Writing back store idx:%i PC:%#x "
 628                 "to Addr:%#x, data:%#x [sn:%lli]\n",
 629                 inst->sqIdx,inst->readPC(),
 630                 req->paddr, *(req->data),
 631                 inst->seqNum);
 632
 633         if (dcacheInterface) {
 634             assert(!req->completionEvent);
 635             StoreCompletionEvent *store_event = new
 636                 StoreCompletionEvent(inst, be, NULL, this);
 637             req->completionEvent = store_event;
 638
 639             MemAccessResult result = dcacheInterface->access(req);
 640
 641             if (isStalled() &&
 642                 inst->seqNum == stallingStoreIsn) {
 643                 DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 644                         "load [sn:%lli]\n",
 645                         stallingStoreIsn, (*stallingLoad)->seqNum);
 646                 stalled = false;
 647                 stallingStoreIsn = 0;
 648                 be->replayMemInst((*stallingLoad));
 649             }
 650
 651             if (result != MA_HIT && dcacheInterface->doEvents()) {
 652                 store_event->miss = true;
 653                 typename BackEnd::LdWritebackEvent *wb = NULL;
 654                 if (req->flags & LOCKED) {
 655                     wb = new typename BackEnd::LdWritebackEvent(inst,
 656                                                             be);
 657                     store_event->wbEvent = wb;
 658                 }
 659
 660                 DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
 661
 662 //                DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
 663 //                        inst->seqNum);
 664
 665                 be->addDcacheMiss(inst);
 666
 667                 lastDcacheStall = curTick;
 668
 669                 _status = DcacheMissStall;
 670
 671                 // Increment stat here or something
 672
 673                 sq_it--;
 674             } else {
 675                 DPRINTF(OzoneLSQ,"D-Cache: Write Hit on idx:%i !\n",
 676                         inst->sqIdx);
 677
 678 //                DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 679 //                        inst->seqNum);
 680
 681                 if (req->flags & LOCKED) {
 682                     // Stx_C does not generate a system port
 683                     // transaction in the 21264, but that might be
 684                     // hard to accomplish in this model.
 685
 686                     typename BackEnd::LdWritebackEvent *wb =
 687                         new typename BackEnd::LdWritebackEvent(inst,
 688                                                                be);
 689                     store_event->wbEvent = wb;
 690                 }
 691                 sq_it--;
 692             }
 693         } else {
 694             panic("Must HAVE DCACHE!!!!!\n");
 695         }
 696 */
 697     }
 698
 699     // Not sure this should set it to 0.
 700     usedPorts = 0;
 701
 702     assert(stores >= 0 && storesToWB >= 0);
 703 }
 704
 705 template <class Impl>
 706 void
 707 OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
 708 {
 709     DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
 710             "(Loads:%i Stores:%i)\n",squashed_num,loads,stores);
 711
 712
 713     LQIt lq_it = loadQueue.begin();
 714
 715     while (loads != 0 && (*lq_it)->seqNum > squashed_num) {
 716         assert(!loadQueue.empty());
 717         // Clear the smart pointer to make sure it is decremented.
 718         DPRINTF(OzoneLSQ,"Load Instruction PC %#x squashed, "
 719                 "[sn:%lli]\n",
 720                 (*lq_it)->readPC(),
 721                 (*lq_it)->seqNum);
 722
 723         if (isStalled() && lq_it == stallingLoad) {
 724             stalled = false;
 725             stallingStoreIsn = 0;
 726             stallingLoad = NULL;
 727         }
 728
 729         --loads;
 730
 731         // Inefficient!
 732         LQHashIt lq_hash_it = LQItHash.find((*lq_it)->lqIdx);
 733         assert(lq_hash_it != LQItHash.end());
 734         LQItHash.erase(lq_hash_it);
 735         LQIndices.push((*lq_it)->lqIdx);
 736         loadQueue.erase(lq_it++);
 737     }
 738
 739     if (isLoadBlocked) {
 740         if (squashed_num < blockedLoadSeqNum) {
 741             isLoadBlocked = false;
 742             loadBlockedHandled = false;
 743             blockedLoadSeqNum = 0;
 744         }
 745     }
 746
 747     SQIt sq_it = storeQueue.begin();
 748
 749     while (stores != 0 && (*sq_it).inst->seqNum > squashed_num) {
 750         assert(!storeQueue.empty());
 751
 752         if ((*sq_it).canWB) {
 753             break;
 754         }
 755
 756         // Clear the smart pointer to make sure it is decremented.
 757         DPRINTF(OzoneLSQ,"Store Instruction PC %#x idx:%i squashed [sn:%lli]\n",
 758                 (*sq_it).inst->readPC(), (*sq_it).inst->sqIdx,
 759                 (*sq_it).inst->seqNum);
 760
 761         // I don't think this can happen.  It should have been cleared by the
 762         // stalling load.
 763         if (isStalled() &&
 764             (*sq_it).inst->seqNum == stallingStoreIsn) {
 765             panic("Is stalled should have been cleared by stalling load!\n");
 766             stalled = false;
 767             stallingStoreIsn = 0;
 768         }
 769
 770         SQHashIt sq_hash_it = SQItHash.find((*sq_it).inst->sqIdx);
 771         assert(sq_hash_it != SQItHash.end());
 772         SQItHash.erase(sq_hash_it);
 773         SQIndices.push((*sq_it).inst->sqIdx);
 774         (*sq_it).inst = NULL;
 775         (*sq_it).canWB = 0;
 776         (*sq_it).req = NULL;
 777         --stores;
 778         storeQueue.erase(sq_it++);
 779     }
 780 }
 781
 782 template <class Impl>
 783 void
 784 OzoneLWLSQ<Impl>::dumpInsts()
 785 {
 786     cprintf("Load store queue: Dumping instructions.\n");
 787     cprintf("Load queue size: %i\n", loads);
 788     cprintf("Load queue: ");
 789
 790     LQIt lq_it = --(loadQueue.end());
 791
 792     while (lq_it != loadQueue.end() && (*lq_it)) {
 793         cprintf("[sn:%lli] %#x ", (*lq_it)->seqNum,
 794                 (*lq_it)->readPC());
 795
 796         lq_it--;
 797     }
 798
 799     cprintf("\nStore queue size: %i\n", stores);
 800     cprintf("Store queue: ");
 801
 802     SQIt sq_it = --(storeQueue.end());
 803
 804     while (sq_it != storeQueue.end() && (*sq_it).inst) {
 805         cprintf("[sn:%lli]\nPC:%#x\nSize:%i\nCommitted:%i\nCompleted:%i\ncanWB:%i\n",
 806                 (*sq_it).inst->seqNum,
 807                 (*sq_it).inst->readPC(),
 808                 (*sq_it).size,
 809                 (*sq_it).committed,
 810                 (*sq_it).completed,
 811                 (*sq_it).canWB);
 812
 813         sq_it--;
 814     }
 815
 816     cprintf("\n");
 817 }
 818
 819 template <class Impl>
 820 void
 821 OzoneLWLSQ<Impl>::storePostSend(Packet *pkt, DynInstPtr &inst)
 822 {
 823     if (isStalled() &&
 824         inst->seqNum == stallingStoreIsn) {
 825         DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 826                 "load [sn:%lli]\n",
 827                 stallingStoreIsn, (*stallingLoad)->seqNum);
 828         stalled = false;
 829         stallingStoreIsn = 0;
 830         be->replayMemInst((*stallingLoad));
 831     }
 832
 833     if (!inst->isStoreConditional()) {
 834         // The store is basically completed at this time. This
 835         // only works so long as the checker doesn't try to
 836         // verify the value in memory for stores.
 837         inst->setCompleted();
 838 #if USE_CHECKER
 839         if (cpu->checker) {
 840             cpu->checker->verify(inst);
 841         }
 842 #endif
 843     }
 844
 845     if (pkt->result != Packet::Success) {
 846         DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
 847
 848         DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
 849                 inst->seqNum);
 850
 851         //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
 852
 853         //DPRINTF(OzoneLWLSQ, "Added MSHR. count = %i\n",mshrSeqNums.size());
 854
 855         // @todo: Increment stat here.
 856     } else {
 857         DPRINTF(OzoneLSQ,"D-Cache: Write Hit!\n");
 858
 859         DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 860                 inst->seqNum);
 861     }
 862 }
 863
 864 template <class Impl>
 865 void
 866 OzoneLWLSQ<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
 867 {
 868     // Squashed instructions do not need to complete their access.
 869     if (inst->isSquashed()) {
 870         assert(!inst->isStore());
 871         return;
 872     }
 873
 874     if (!inst->isExecuted()) {
 875         inst->setExecuted();
 876
 877         // Complete access to copy data to proper place.
 878         inst->completeAcc(pkt);
 879     }
 880
 881     // Need to insert instruction into queue to commit
 882     be->instToCommit(inst);
 883 }
 884
 885 template <class Impl>
 886 void
 887 OzoneLWLSQ<Impl>::completeStore(int store_idx)
 888 {
 889     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 890     assert(sq_hash_it != SQItHash.end());
 891     SQIt sq_it = (*sq_hash_it).second;
 892
 893     assert((*sq_it).inst);
 894     (*sq_it).completed = true;
 895     DynInstPtr inst = (*sq_it).inst;
 896
 897     --storesToWB;
 898
 899     if (isStalled() &&
 900         inst->seqNum == stallingStoreIsn) {
 901         DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 902                 "load [sn:%lli]\n",
 903                 stallingStoreIsn, (*stallingLoad)->seqNum);
 904         stalled = false;
 905         stallingStoreIsn = 0;
 906         be->replayMemInst((*stallingLoad));
 907     }
 908
 909     DPRINTF(OzoneLSQ, "Completing store idx:%i [sn:%lli], storesToWB:%i\n",
 910             inst->sqIdx, inst->seqNum, storesToWB);
 911
 912     assert(!storeQueue.empty());
 913     SQItHash.erase(sq_hash_it);
 914     SQIndices.push(inst->sqIdx);
 915     storeQueue.erase(sq_it);
 916     --stores;
 917
 918     inst->setCompleted();
 919 #if USE_CHECKER
 920     if (cpu->checker) {
 921         cpu->checker->verify(inst);
 922     }
 923 #endif
 924 }
 925
 926 template <class Impl>
 927 void
 928 OzoneLWLSQ<Impl>::recvRetry()
 929 {
 930     panic("Unimplemented!");
 931 }
 932
 933 template <class Impl>
 934 void
 935 OzoneLWLSQ<Impl>::switchOut()
 936 {
 937     assert(storesToWB == 0);
 938     switchedOut = true;
 939
 940     // Clear the queue to free up resources
 941     storeQueue.clear();
 942     loadQueue.clear();
 943     loads = stores = storesToWB = 0;
 944 }
 945
 946 template <class Impl>
 947 void
 948 OzoneLWLSQ<Impl>::takeOverFrom(ThreadContext *old_tc)
 949 {
 950     // Clear out any old state. May be redundant if this is the first time
 951     // the CPU is being used.
 952     stalled = false;
 953     isLoadBlocked = false;
 954     loadBlockedHandled = false;
 955     switchedOut = false;
 956
 957     // Could do simple checks here to see if indices are on twice
 958     while (!LQIndices.empty())
 959         LQIndices.pop();
 960     while (!SQIndices.empty())
 961         SQIndices.pop();
 962
 963     for (int i = 0; i < LQEntries * 2; i++) {
 964         LQIndices.push(i);
 965         SQIndices.push(i);
 966     }
 967
 968     usedPorts = 0;
 969
 970     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 971
 972     blockedLoadSeqNum = 0;
 973 }