src/cpu/ozone/lw_lsq_impl.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "config/use_checker.hh"
  32
  33 #include "arch/faults.hh"
  34 #include "base/str.hh"
  35 #include "cpu/ozone/lw_lsq.hh"
  36 #include "cpu/checker/cpu.hh"
  37
  38 template<class Impl>
  39 OzoneLWLSQ<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
  40                                                  OzoneLWLSQ *lsq_ptr)
  41     : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
  42 {
  43     this->setFlags(Event::AutoDelete);
  44 }
  45
  46 template<class Impl>
  47 void
  48 OzoneLWLSQ<Impl>::WritebackEvent::process()
  49 {
  50     if (!lsqPtr->isSwitchedOut()) {
  51         lsqPtr->writeback(inst, pkt);
  52     }
  53     delete pkt;
  54 }
  55
  56 template<class Impl>
  57 const char *
  58 OzoneLWLSQ<Impl>::WritebackEvent::description()
  59 {
  60     return "Store writeback event";
  61 }
  62
  63 template <class Impl>
  64 Tick
  65 OzoneLWLSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
  66 {
  67     panic("O3CPU model does not work with atomic mode!");
  68     return curTick;
  69 }
  70
  71 template <class Impl>
  72 void
  73 OzoneLWLSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
  74 {
  75     warn("O3CPU doesn't update things on a recvFunctional");
  76 }
  77
  78 template <class Impl>
  79 void
  80 OzoneLWLSQ<Impl>::DcachePort::recvStatusChange(Status status)
  81 {
  82     if (status == RangeChange)
  83         return;
  84
  85     panic("O3CPU doesn't expect recvStatusChange callback!");
  86 }
  87
  88 template <class Impl>
  89 bool
  90 OzoneLWLSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
  91 {
  92     lsq->completeDataAccess(pkt);
  93     return true;
  94 }
  95
  96 template <class Impl>
  97 void
  98 OzoneLWLSQ<Impl>::DcachePort::recvRetry()
  99 {
 100     lsq->recvRetry();
 101 }
 102
 103 template<class Impl>
 104 void
 105 OzoneLWLSQ<Impl>::completeDataAccess(PacketPtr pkt)
 106 {
 107     LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
 108     DynInstPtr inst = state->inst;
 109     DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
 110     DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
 111
 112     //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
 113
 114     if (isSwitchedOut() || inst->isSquashed()) {
 115         delete state;
 116         delete pkt;
 117         return;
 118     } else {
 119         if (!state->noWB) {
 120             writeback(inst, pkt);
 121         }
 122
 123         if (inst->isStore()) {
 124             completeStore(inst);
 125         }
 126     }
 127
 128     delete state;
 129     delete pkt;
 130 }
 131
 132 template <class Impl>
 133 OzoneLWLSQ<Impl>::OzoneLWLSQ()
 134     : switchedOut(false), dcachePort(this), loads(0), stores(0),
 135       storesToWB(0), storesInFlight(0), stalled(false), isStoreBlocked(false),
 136       isLoadBlocked(false), loadBlockedHandled(false)
 137 {
 138 }
 139
 140 template<class Impl>
 141 void
 142 OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
 143                        unsigned maxSQEntries, unsigned id)
 144 {
 145     DPRINTF(OzoneLSQ, "Creating OzoneLWLSQ%i object.\n",id);
 146
 147     lsqID = id;
 148
 149     LQEntries = maxLQEntries;
 150     SQEntries = maxSQEntries;
 151
 152     for (int i = 0; i < LQEntries * 2; i++) {
 153         LQIndices.push(i);
 154         SQIndices.push(i);
 155     }
 156
 157     usedPorts = 0;
 158     cachePorts = params->cachePorts;
 159
 160     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 161
 162     blockedLoadSeqNum = 0;
 163 }
 164
 165 template<class Impl>
 166 std::string
 167 OzoneLWLSQ<Impl>::name() const
 168 {
 169     return "lsqunit";
 170 }
 171
 172 template<class Impl>
 173 void
 174 OzoneLWLSQ<Impl>::regStats()
 175 {
 176     lsqMemOrderViolation
 177         .name(name() + ".memOrderViolation")
 178         .desc("Number of memory ordering violations");
 179 }
 180
 181 template<class Impl>
 182 void
 183 OzoneLWLSQ<Impl>::setCPU(OzoneCPU *cpu_ptr)
 184 {
 185     cpu = cpu_ptr;
 186     dcachePort.setName(this->name() + "-dport");
 187
 188 #if USE_CHECKER
 189     if (cpu->checker) {
 190         cpu->checker->setDcachePort(&dcachePort);
 191     }
 192 #endif
 193 }
 194
 195 template<class Impl>
 196 void
 197 OzoneLWLSQ<Impl>::clearLQ()
 198 {
 199     loadQueue.clear();
 200 }
 201
 202 template<class Impl>
 203 void
 204 OzoneLWLSQ<Impl>::clearSQ()
 205 {
 206     storeQueue.clear();
 207 }
 208 /*
 209 template<class Impl>
 210 void
 211 OzoneLWLSQ<Impl>::setPageTable(PageTable *pt_ptr)
 212 {
 213     DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
 214     pTable = pt_ptr;
 215 }
 216 */
 217 template<class Impl>
 218 void
 219 OzoneLWLSQ<Impl>::resizeLQ(unsigned size)
 220 {
 221     assert( size >= LQEntries);
 222
 223     if (size > LQEntries) {
 224         while (size > loadQueue.size()) {
 225             DynInstPtr dummy;
 226             loadQueue.push_back(dummy);
 227             LQEntries++;
 228         }
 229     } else {
 230         LQEntries = size;
 231     }
 232
 233 }
 234
 235 template<class Impl>
 236 void
 237 OzoneLWLSQ<Impl>::resizeSQ(unsigned size)
 238 {
 239     if (size > SQEntries) {
 240         while (size > storeQueue.size()) {
 241             SQEntry dummy;
 242             storeQueue.push_back(dummy);
 243             SQEntries++;
 244         }
 245     } else {
 246         SQEntries = size;
 247     }
 248 }
 249
 250 template <class Impl>
 251 void
 252 OzoneLWLSQ<Impl>::insert(DynInstPtr &inst)
 253 {
 254     // Make sure we really have a memory reference.
 255     assert(inst->isMemRef());
 256
 257     // Make sure it's one of the two classes of memory references.
 258     assert(inst->isLoad() || inst->isStore());
 259
 260     if (inst->isLoad()) {
 261         insertLoad(inst);
 262     } else {
 263         insertStore(inst);
 264     }
 265 }
 266
 267 template <class Impl>
 268 void
 269 OzoneLWLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
 270 {
 271     assert(loads < LQEntries * 2);
 272     assert(!LQIndices.empty());
 273     int load_index = LQIndices.front();
 274     LQIndices.pop();
 275
 276     DPRINTF(OzoneLSQ, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
 277             load_inst->readPC(), load_index, load_inst->seqNum);
 278
 279     load_inst->lqIdx = load_index;
 280
 281     loadQueue.push_front(load_inst);
 282     LQItHash[load_index] = loadQueue.begin();
 283
 284     ++loads;
 285 }
 286
 287 template <class Impl>
 288 void
 289 OzoneLWLSQ<Impl>::insertStore(DynInstPtr &store_inst)
 290 {
 291     // Make sure it is not full before inserting an instruction.
 292     assert(stores - storesToWB < SQEntries);
 293
 294     assert(!SQIndices.empty());
 295     int store_index = SQIndices.front();
 296     SQIndices.pop();
 297
 298     DPRINTF(OzoneLSQ, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
 299             store_inst->readPC(), store_index, store_inst->seqNum);
 300
 301     store_inst->sqIdx = store_index;
 302     SQEntry entry(store_inst);
 303     if (loadQueue.empty()) {
 304         entry.lqIt = loadQueue.end();
 305     } else {
 306         entry.lqIt = loadQueue.begin();
 307     }
 308     storeQueue.push_front(entry);
 309
 310     SQItHash[store_index] = storeQueue.begin();
 311
 312     ++stores;
 313 }
 314
 315 template <class Impl>
 316 typename Impl::DynInstPtr
 317 OzoneLWLSQ<Impl>::getMemDepViolator()
 318 {
 319     DynInstPtr temp = memDepViolator;
 320
 321     memDepViolator = NULL;
 322
 323     return temp;
 324 }
 325
 326 template <class Impl>
 327 unsigned
 328 OzoneLWLSQ<Impl>::numFreeEntries()
 329 {
 330     unsigned free_lq_entries = LQEntries - loads;
 331     unsigned free_sq_entries = SQEntries - (stores + storesInFlight);
 332
 333     // Both the LQ and SQ entries have an extra dummy entry to differentiate
 334     // empty/full conditions.  Subtract 1 from the free entries.
 335     if (free_lq_entries < free_sq_entries) {
 336         return free_lq_entries - 1;
 337     } else {
 338         return free_sq_entries - 1;
 339     }
 340 }
 341
 342 template <class Impl>
 343 int
 344 OzoneLWLSQ<Impl>::numLoadsReady()
 345 {
 346     int retval = 0;
 347     LQIt lq_it = loadQueue.begin();
 348     LQIt end_it = loadQueue.end();
 349
 350     while (lq_it != end_it) {
 351         if ((*lq_it)->readyToIssue()) {
 352             ++retval;
 353         }
 354     }
 355
 356     return retval;
 357 }
 358
 359 template <class Impl>
 360 Fault
 361 OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst)
 362 {
 363     // Execute a specific load.
 364     Fault load_fault = NoFault;
 365
 366     DPRINTF(OzoneLSQ, "Executing load PC %#x, [sn:%lli]\n",
 367             inst->readPC(),inst->seqNum);
 368
 369     // Make sure it's really in the list.
 370     // Normally it should always be in the list.  However,
 371     /* due to a syscall it may not be the list.
 372 #ifdef DEBUG
 373     int i = loadHead;
 374     while (1) {
 375         if (i == loadTail && !find(inst)) {
 376             assert(0 && "Load not in the queue!");
 377         } else if (loadQueue[i] == inst) {
 378             break;
 379         }
 380
 381         i = i + 1;
 382         if (i >= LQEntries) {
 383             i = 0;
 384         }
 385     }
 386 #endif // DEBUG*/
 387
 388     load_fault = inst->initiateAcc();
 389
 390     // Might want to make sure that I'm not overwriting a previously faulting
 391     // instruction that hasn't been checked yet.
 392     // Actually probably want the oldest faulting load
 393     if (load_fault != NoFault) {
 394         DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum);
 395         if (!(inst->req->isUncacheable() && !inst->isAtCommit())) {
 396             inst->setExecuted();
 397         }
 398         // Maybe just set it as can commit here, although that might cause
 399         // some other problems with sending traps to the ROB too quickly.
 400         be->instToCommit(inst);
 401 //        iewStage->activityThisCycle();
 402     }
 403
 404     return load_fault;
 405 }
 406
 407 template <class Impl>
 408 Fault
 409 OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
 410 {
 411     // Make sure that a store exists.
 412     assert(stores != 0);
 413
 414     int store_idx = store_inst->sqIdx;
 415     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 416     assert(sq_hash_it != SQItHash.end());
 417     DPRINTF(OzoneLSQ, "Executing store PC %#x [sn:%lli]\n",
 418             store_inst->readPC(), store_inst->seqNum);
 419
 420     SQIt sq_it = (*sq_hash_it).second;
 421
 422     Fault store_fault = store_inst->initiateAcc();
 423
 424     // Store size should now be available.  Use it to get proper offset for
 425     // addr comparisons.
 426     int size = (*sq_it).size;
 427
 428     if (size == 0) {
 429         DPRINTF(OzoneLSQ,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
 430                 store_inst->readPC(),store_inst->seqNum);
 431
 432         return store_fault;
 433     }
 434
 435     assert(store_fault == NoFault);
 436
 437     if (!storeFaultInst) {
 438         if (store_fault != NoFault) {
 439             panic("Fault in a store instruction!");
 440             storeFaultInst = store_inst;
 441         } else if (store_inst->isStoreConditional()) {
 442             // Store conditionals need to set themselves as able to
 443             // writeback if we haven't had a fault by here.
 444             (*sq_it).canWB = true;
 445
 446             ++storesToWB;
 447             DPRINTF(OzoneLSQ, "Nonspeculative store! storesToWB:%i\n",
 448                     storesToWB);
 449         }
 450     }
 451
 452     LQIt lq_it = --(loadQueue.end());
 453
 454     if (!memDepViolator) {
 455         while (lq_it != loadQueue.end()) {
 456             if ((*lq_it)->seqNum < store_inst->seqNum) {
 457                 lq_it--;
 458                 continue;
 459             }
 460             // Actually should only check loads that have actually executed
 461             // Might be safe because effAddr is set to InvalAddr when the
 462             // dyn inst is created.
 463
 464             // Must actually check all addrs in the proper size range
 465             // Which is more correct than needs to be.  What if for now we just
 466             // assume all loads are quad-word loads, and do the addr based
 467             // on that.
 468             // @todo: Fix this, magic number being used here
 469             if (((*lq_it)->effAddr >> 8) ==
 470                 (store_inst->effAddr >> 8)) {
 471                 // A load incorrectly passed this store.  Squash and refetch.
 472                 // For now return a fault to show that it was unsuccessful.
 473                 memDepViolator = (*lq_it);
 474                 ++lsqMemOrderViolation;
 475
 476                 return TheISA::genMachineCheckFault();
 477             }
 478
 479             lq_it--;
 480         }
 481
 482         // If we've reached this point, there was no violation.
 483         memDepViolator = NULL;
 484     }
 485
 486     return store_fault;
 487 }
 488
 489 template <class Impl>
 490 void
 491 OzoneLWLSQ<Impl>::commitLoad()
 492 {
 493     assert(!loadQueue.empty());
 494
 495     DPRINTF(OzoneLSQ, "[sn:%lli] Committing head load instruction, PC %#x\n",
 496             loadQueue.back()->seqNum, loadQueue.back()->readPC());
 497
 498     LQIndices.push(loadQueue.back()->lqIdx);
 499     LQItHash.erase(loadQueue.back()->lqIdx);
 500
 501     loadQueue.pop_back();
 502
 503     --loads;
 504 }
 505
 506 template <class Impl>
 507 void
 508 OzoneLWLSQ<Impl>::commitLoads(InstSeqNum &youngest_inst)
 509 {
 510     assert(loads == 0 || !loadQueue.empty());
 511
 512     while (loads != 0 &&
 513            loadQueue.back()->seqNum <= youngest_inst) {
 514         commitLoad();
 515     }
 516 }
 517
 518 template <class Impl>
 519 void
 520 OzoneLWLSQ<Impl>::commitStores(InstSeqNum &youngest_inst)
 521 {
 522     assert(stores == 0 || !storeQueue.empty());
 523
 524     SQIt sq_it = --(storeQueue.end());
 525     while (!storeQueue.empty() && sq_it != storeQueue.end()) {
 526         assert((*sq_it).inst);
 527         if (!(*sq_it).canWB) {
 528             if ((*sq_it).inst->seqNum > youngest_inst) {
 529                 break;
 530             }
 531             ++storesToWB;
 532
 533             DPRINTF(OzoneLSQ, "Marking store as able to write back, PC "
 534                     "%#x [sn:%lli], storesToWB:%i\n",
 535                     (*sq_it).inst->readPC(),
 536                     (*sq_it).inst->seqNum,
 537                     storesToWB);
 538
 539             (*sq_it).canWB = true;
 540         }
 541
 542         sq_it--;
 543     }
 544 }
 545
 546 template <class Impl>
 547 void
 548 OzoneLWLSQ<Impl>::writebackStores()
 549 {
 550     SQIt sq_it = --(storeQueue.end());
 551     while (storesToWB > 0 &&
 552            sq_it != storeQueue.end() &&
 553            (*sq_it).inst &&
 554            (*sq_it).canWB &&
 555            usedPorts < cachePorts) {
 556
 557         if (isStoreBlocked) {
 558             DPRINTF(OzoneLSQ, "Unable to write back any more stores, cache"
 559                     " is blocked!\n");
 560             break;
 561         }
 562
 563         DynInstPtr inst = (*sq_it).inst;
 564
 565         if ((*sq_it).size == 0 && !(*sq_it).completed) {
 566             sq_it--;
 567             removeStore(inst->sqIdx);
 568             completeStore(inst);
 569             continue;
 570         }
 571
 572         if (inst->isDataPrefetch() || (*sq_it).committed) {
 573             sq_it--;
 574             continue;
 575         }
 576
 577         ++usedPorts;
 578
 579         assert((*sq_it).req);
 580         assert(!(*sq_it).committed);
 581
 582         Request *req = (*sq_it).req;
 583         (*sq_it).committed = true;
 584
 585         assert(!inst->memData);
 586         inst->memData = new uint8_t[64];
 587         memcpy(inst->memData, (uint8_t *)&(*sq_it).data,
 588                req->getSize());
 589
 590         PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
 591         data_pkt->dataStatic(inst->memData);
 592
 593         LSQSenderState *state = new LSQSenderState;
 594         state->isLoad = false;
 595         state->idx = inst->sqIdx;
 596         state->inst = inst;
 597         data_pkt->senderState = state;
 598
 599         DPRINTF(OzoneLSQ, "D-Cache: Writing back store PC:%#x "
 600                 "to Addr:%#x, data:%#x [sn:%lli]\n",
 601                 (*sq_it).inst->readPC(),
 602                 req->getPaddr(), *(inst->memData),
 603                 inst->seqNum);
 604
 605         // @todo: Remove this SC hack once the memory system handles it.
 606         if (req->isLocked()) {
 607             if (req->isUncacheable()) {
 608                 req->setScResult(2);
 609             } else {
 610                 if (cpu->lockFlag) {
 611                     req->setScResult(1);
 612                 } else {
 613                     req->setScResult(0);
 614                     // Hack: Instantly complete this store.
 615                     completeDataAccess(data_pkt);
 616                     --sq_it;
 617                     continue;
 618                 }
 619             }
 620         } else {
 621             // Non-store conditionals do not need a writeback.
 622             state->noWB = true;
 623         }
 624
 625         if (!dcachePort.sendTiming(data_pkt)) {
 626             // Need to handle becoming blocked on a store.
 627             isStoreBlocked = true;
 628             assert(retryPkt == NULL);
 629             retryPkt = data_pkt;
 630         } else {
 631             storePostSend(data_pkt, inst);
 632             --sq_it;
 633         }
 634 /*
 635         DPRINTF(OzoneLSQ, "D-Cache: Writing back store idx:%i PC:%#x "
 636                 "to Addr:%#x, data:%#x [sn:%lli]\n",
 637                 inst->sqIdx,inst->readPC(),
 638                 req->paddr, *(req->data),
 639                 inst->seqNum);
 640         DPRINTF(OzoneLSQ, "StoresInFlight: %i\n",
 641                 storesInFlight + 1);
 642
 643         if (dcacheInterface) {
 644             assert(!req->completionEvent);
 645             StoreCompletionEvent *store_event = new
 646                 StoreCompletionEvent(inst, be, NULL, this);
 647             req->completionEvent = store_event;
 648
 649             MemAccessResult result = dcacheInterface->access(req);
 650
 651             if (isStalled() &&
 652                 inst->seqNum == stallingStoreIsn) {
 653                 DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 654                         "load [sn:%lli]\n",
 655                         stallingStoreIsn, (*stallingLoad)->seqNum);
 656                 stalled = false;
 657                 stallingStoreIsn = 0;
 658                 be->replayMemInst((*stallingLoad));
 659             }
 660
 661             if (result != MA_HIT && dcacheInterface->doEvents()) {
 662                 store_event->miss = true;
 663                 typename BackEnd::LdWritebackEvent *wb = NULL;
 664                 if (req->isLocked()) {
 665                     wb = new typename BackEnd::LdWritebackEvent(inst,
 666                                                             be);
 667                     store_event->wbEvent = wb;
 668                 }
 669
 670                 DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
 671
 672 //                DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
 673 //                        inst->seqNum);
 674
 675                 be->addDcacheMiss(inst);
 676
 677                 lastDcacheStall = curTick;
 678
 679                 _status = DcacheMissStall;
 680
 681                 // Increment stat here or something
 682
 683                 sq_it--;
 684             } else {
 685                 DPRINTF(OzoneLSQ,"D-Cache: Write Hit on idx:%i !\n",
 686                         inst->sqIdx);
 687
 688 //                DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 689 //                        inst->seqNum);
 690
 691                 if (req->isLocked()) {
 692                     // Stx_C does not generate a system port
 693                     // transaction in the 21264, but that might be
 694                     // hard to accomplish in this model.
 695
 696                     typename BackEnd::LdWritebackEvent *wb =
 697                         new typename BackEnd::LdWritebackEvent(inst,
 698                                                                be);
 699                     store_event->wbEvent = wb;
 700                 }
 701                 sq_it--;
 702             }
 703             ++storesInFlight;
 704 //            removeStore(inst->sqIdx);
 705         } else {
 706             panic("Must HAVE DCACHE!!!!!\n");
 707         }
 708 */
 709     }
 710
 711     // Not sure this should set it to 0.
 712     usedPorts = 0;
 713
 714     assert(stores >= 0 && storesToWB >= 0);
 715 }
 716
 717 template <class Impl>
 718 void
 719 OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
 720 {
 721     DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
 722             "(Loads:%i Stores:%i)\n",squashed_num,loads,stores+storesInFlight);
 723
 724
 725     LQIt lq_it = loadQueue.begin();
 726
 727     while (loads != 0 && (*lq_it)->seqNum > squashed_num) {
 728         assert(!loadQueue.empty());
 729         // Clear the smart pointer to make sure it is decremented.
 730         DPRINTF(OzoneLSQ,"Load Instruction PC %#x squashed, "
 731                 "[sn:%lli]\n",
 732                 (*lq_it)->readPC(),
 733                 (*lq_it)->seqNum);
 734
 735         if (isStalled() && lq_it == stallingLoad) {
 736             stalled = false;
 737             stallingStoreIsn = 0;
 738             stallingLoad = NULL;
 739         }
 740
 741         --loads;
 742
 743         // Inefficient!
 744         LQHashIt lq_hash_it = LQItHash.find((*lq_it)->lqIdx);
 745         assert(lq_hash_it != LQItHash.end());
 746         LQItHash.erase(lq_hash_it);
 747         LQIndices.push((*lq_it)->lqIdx);
 748         loadQueue.erase(lq_it++);
 749     }
 750
 751     if (isLoadBlocked) {
 752         if (squashed_num < blockedLoadSeqNum) {
 753             isLoadBlocked = false;
 754             loadBlockedHandled = false;
 755             blockedLoadSeqNum = 0;
 756         }
 757     }
 758
 759     SQIt sq_it = storeQueue.begin();
 760
 761     while (stores != 0 && (*sq_it).inst->seqNum > squashed_num) {
 762         assert(!storeQueue.empty());
 763
 764         if ((*sq_it).canWB) {
 765             break;
 766         }
 767
 768         // Clear the smart pointer to make sure it is decremented.
 769         DPRINTF(OzoneLSQ,"Store Instruction PC %#x idx:%i squashed [sn:%lli]\n",
 770                 (*sq_it).inst->readPC(), (*sq_it).inst->sqIdx,
 771                 (*sq_it).inst->seqNum);
 772
 773         // I don't think this can happen.  It should have been cleared by the
 774         // stalling load.
 775         if (isStalled() &&
 776             (*sq_it).inst->seqNum == stallingStoreIsn) {
 777             panic("Is stalled should have been cleared by stalling load!\n");
 778             stalled = false;
 779             stallingStoreIsn = 0;
 780         }
 781
 782         SQHashIt sq_hash_it = SQItHash.find((*sq_it).inst->sqIdx);
 783         assert(sq_hash_it != SQItHash.end());
 784         SQItHash.erase(sq_hash_it);
 785         SQIndices.push((*sq_it).inst->sqIdx);
 786         (*sq_it).inst = NULL;
 787         (*sq_it).canWB = 0;
 788         (*sq_it).req = NULL;
 789         --stores;
 790         storeQueue.erase(sq_it++);
 791     }
 792 }
 793
 794 template <class Impl>
 795 void
 796 OzoneLWLSQ<Impl>::dumpInsts()
 797 {
 798     cprintf("Load store queue: Dumping instructions.\n");
 799     cprintf("Load queue size: %i\n", loads);
 800     cprintf("Load queue: ");
 801
 802     LQIt lq_it = --(loadQueue.end());
 803
 804     while (lq_it != loadQueue.end() && (*lq_it)) {
 805         cprintf("[sn:%lli] %#x ", (*lq_it)->seqNum,
 806                 (*lq_it)->readPC());
 807
 808         lq_it--;
 809     }
 810
 811     cprintf("\nStore queue size: %i\n", stores);
 812     cprintf("Store queue: ");
 813
 814     SQIt sq_it = --(storeQueue.end());
 815
 816     while (sq_it != storeQueue.end() && (*sq_it).inst) {
 817         cprintf("[sn:%lli]\nPC:%#x\nSize:%i\nCommitted:%i\nCompleted:%i\ncanWB:%i\n",
 818                 (*sq_it).inst->seqNum,
 819                 (*sq_it).inst->readPC(),
 820                 (*sq_it).size,
 821                 (*sq_it).committed,
 822                 (*sq_it).completed,
 823                 (*sq_it).canWB);
 824
 825         sq_it--;
 826     }
 827
 828     cprintf("\n");
 829 }
 830
 831 template <class Impl>
 832 void
 833 OzoneLWLSQ<Impl>::storePostSend(PacketPtr pkt, DynInstPtr &inst)
 834 {
 835     if (isStalled() &&
 836         inst->seqNum == stallingStoreIsn) {
 837         DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 838                 "load [sn:%lli]\n",
 839                 stallingStoreIsn, (*stallingLoad)->seqNum);
 840         stalled = false;
 841         stallingStoreIsn = 0;
 842         be->replayMemInst((*stallingLoad));
 843     }
 844
 845     if (!inst->isStoreConditional()) {
 846         // The store is basically completed at this time. This
 847         // only works so long as the checker doesn't try to
 848         // verify the value in memory for stores.
 849         inst->setCompleted();
 850 #if USE_CHECKER
 851         if (cpu->checker) {
 852             cpu->checker->verify(inst);
 853         }
 854 #endif
 855     }
 856
 857     if (pkt->result != Packet::Success) {
 858         DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
 859
 860         DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
 861                 inst->seqNum);
 862
 863         //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
 864
 865         //DPRINTF(OzoneLWLSQ, "Added MSHR. count = %i\n",mshrSeqNums.size());
 866
 867         // @todo: Increment stat here.
 868     } else {
 869         DPRINTF(OzoneLSQ,"D-Cache: Write Hit!\n");
 870
 871         DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
 872                 inst->seqNum);
 873     }
 874 }
 875
 876 template <class Impl>
 877 void
 878 OzoneLWLSQ<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
 879 {
 880     // Squashed instructions do not need to complete their access.
 881     if (inst->isSquashed()) {
 882         assert(!inst->isStore());
 883         return;
 884     }
 885
 886     if (!inst->isExecuted()) {
 887         inst->setExecuted();
 888
 889         // Complete access to copy data to proper place.
 890         inst->completeAcc(pkt);
 891     }
 892
 893     // Need to insert instruction into queue to commit
 894     be->instToCommit(inst);
 895 }
 896
 897 template <class Impl>
 898 void
 899 OzoneLWLSQ<Impl>::removeStore(int store_idx)
 900 {
 901     SQHashIt sq_hash_it = SQItHash.find(store_idx);
 902     assert(sq_hash_it != SQItHash.end());
 903     SQIt sq_it = (*sq_hash_it).second;
 904
 905     assert((*sq_it).inst);
 906     (*sq_it).completed = true;
 907     DynInstPtr inst = (*sq_it).inst;
 908
 909     if (isStalled() &&
 910         inst->seqNum == stallingStoreIsn) {
 911         DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
 912                 "load [sn:%lli]\n",
 913                 stallingStoreIsn, (*stallingLoad)->seqNum);
 914         stalled = false;
 915         stallingStoreIsn = 0;
 916         be->replayMemInst((*stallingLoad));
 917     }
 918
 919     DPRINTF(OzoneLSQ, "Completing store idx:%i [sn:%lli], storesToWB:%i\n",
 920             inst->sqIdx, inst->seqNum, storesToWB);
 921
 922     assert(!storeQueue.empty());
 923     SQItHash.erase(sq_hash_it);
 924     SQIndices.push(inst->sqIdx);
 925     storeQueue.erase(sq_it);
 926 }
 927
 928 template <class Impl>
 929 void
 930 OzoneLWLSQ<Impl>::completeStore(DynInstPtr &inst)
 931 {
 932     --storesToWB;
 933     --stores;
 934
 935     inst->setCompleted();
 936 #if USE_CHECKER
 937     if (cpu->checker) {
 938         cpu->checker->verify(inst);
 939     }
 940 #endif
 941 }
 942
 943 template <class Impl>
 944 void
 945 OzoneLWLSQ<Impl>::recvRetry()
 946 {
 947     panic("Unimplemented!");
 948 }
 949
 950 template <class Impl>
 951 void
 952 OzoneLWLSQ<Impl>::switchOut()
 953 {
 954     assert(storesToWB == 0);
 955     switchedOut = true;
 956
 957     // Clear the queue to free up resources
 958     assert(stores == 0);
 959     assert(storeQueue.empty());
 960     assert(loads == 0);
 961     assert(loadQueue.empty());
 962     assert(storesInFlight == 0);
 963     storeQueue.clear();
 964     loadQueue.clear();
 965     loads = stores = storesToWB = storesInFlight = 0;
 966 }
 967
 968 template <class Impl>
 969 void
 970 OzoneLWLSQ<Impl>::takeOverFrom(ThreadContext *old_tc)
 971 {
 972     // Clear out any old state. May be redundant if this is the first time
 973     // the CPU is being used.
 974     stalled = false;
 975     isLoadBlocked = false;
 976     loadBlockedHandled = false;
 977     switchedOut = false;
 978
 979     // Could do simple checks here to see if indices are on twice
 980     while (!LQIndices.empty())
 981         LQIndices.pop();
 982     while (!SQIndices.empty())
 983         SQIndices.pop();
 984
 985     for (int i = 0; i < LQEntries * 2; i++) {
 986         LQIndices.push(i);
 987         SQIndices.push(i);
 988     }
 989
 990     usedPorts = 0;
 991
 992     loadFaultInst = storeFaultInst = memDepViolator = NULL;
 993
 994     blockedLoadSeqNum = 0;
 995 }