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31 #include "config/use_checker.hh"
33 #include "arch/faults.hh"
34 #include "base/str.hh"
35 #include "cpu/ozone/lw_lsq.hh"
36 #include "cpu/checker/cpu.hh"
39 OzoneLWLSQ<Impl>::WritebackEvent::WritebackEvent(DynInstPtr &_inst, PacketPtr _pkt,
41 : Event(&mainEventQueue), inst(_inst), pkt(_pkt), lsqPtr(lsq_ptr)
43 this->setFlags(Event::AutoDelete);
48 OzoneLWLSQ<Impl>::WritebackEvent::process()
50 if (!lsqPtr->isSwitchedOut()) {
51 lsqPtr->writeback(inst, pkt);
58 OzoneLWLSQ<Impl>::WritebackEvent::description()
60 return "Store writeback event";
65 OzoneLWLSQ<Impl>::DcachePort::recvAtomic(PacketPtr pkt)
67 panic("O3CPU model does not work with atomic mode!");
73 OzoneLWLSQ<Impl>::DcachePort::recvFunctional(PacketPtr pkt)
75 warn("O3CPU doesn't update things on a recvFunctional");
80 OzoneLWLSQ<Impl>::DcachePort::recvStatusChange(Status status)
82 if (status == RangeChange)
85 panic("O3CPU doesn't expect recvStatusChange callback!");
90 OzoneLWLSQ<Impl>::DcachePort::recvTiming(PacketPtr pkt)
92 lsq->completeDataAccess(pkt);
98 OzoneLWLSQ<Impl>::DcachePort::recvRetry()
105 OzoneLWLSQ<Impl>::completeDataAccess(PacketPtr pkt)
107 LSQSenderState *state = dynamic_cast<LSQSenderState *>(pkt->senderState);
108 DynInstPtr inst = state->inst;
109 DPRINTF(IEW, "Writeback event [sn:%lli]\n", inst->seqNum);
110 DPRINTF(Activity, "Activity: Writeback event [sn:%lli]\n", inst->seqNum);
112 //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum);
114 if (isSwitchedOut() || inst->isSquashed()) {
120 writeback(inst, pkt);
123 if (inst->isStore()) {
132 template <class Impl>
133 OzoneLWLSQ<Impl>::OzoneLWLSQ()
134 : switchedOut(false), dcachePort(this), loads(0), stores(0),
135 storesToWB(0), storesInFlight(0), stalled(false), isStoreBlocked(false),
136 isLoadBlocked(false), loadBlockedHandled(false)
142 OzoneLWLSQ<Impl>::init(Params *params, unsigned maxLQEntries,
143 unsigned maxSQEntries, unsigned id)
145 DPRINTF(OzoneLSQ, "Creating OzoneLWLSQ%i object.\n",id);
149 LQEntries = maxLQEntries;
150 SQEntries = maxSQEntries;
152 for (int i = 0; i < LQEntries * 2; i++) {
160 cachePorts = params->cachePorts;
162 loadFaultInst = storeFaultInst = memDepViolator = NULL;
164 blockedLoadSeqNum = 0;
169 OzoneLWLSQ<Impl>::name() const
176 OzoneLWLSQ<Impl>::regStats()
179 .name(name() + ".memOrderViolation")
180 .desc("Number of memory ordering violations");
185 OzoneLWLSQ<Impl>::setCPU(OzoneCPU *cpu_ptr)
188 dcachePort.setName(this->name() + "-dport");
192 cpu->checker->setDcachePort(&dcachePort);
199 OzoneLWLSQ<Impl>::clearLQ()
206 OzoneLWLSQ<Impl>::clearSQ()
213 OzoneLWLSQ<Impl>::setPageTable(PageTable *pt_ptr)
215 DPRINTF(OzoneLSQ, "Setting the page table pointer.\n");
221 OzoneLWLSQ<Impl>::resizeLQ(unsigned size)
223 assert( size >= LQEntries);
225 if (size > LQEntries) {
226 while (size > loadQueue.size()) {
228 loadQueue.push_back(dummy);
239 OzoneLWLSQ<Impl>::resizeSQ(unsigned size)
241 if (size > SQEntries) {
242 while (size > storeQueue.size()) {
244 storeQueue.push_back(dummy);
252 template <class Impl>
254 OzoneLWLSQ<Impl>::insert(DynInstPtr &inst)
256 // Make sure we really have a memory reference.
257 assert(inst->isMemRef());
259 // Make sure it's one of the two classes of memory references.
260 assert(inst->isLoad() || inst->isStore());
262 if (inst->isLoad()) {
269 template <class Impl>
271 OzoneLWLSQ<Impl>::insertLoad(DynInstPtr &load_inst)
273 assert(loads < LQEntries * 2);
274 assert(!LQIndices.empty());
275 int load_index = LQIndices.front();
278 DPRINTF(OzoneLSQ, "Inserting load PC %#x, idx:%i [sn:%lli]\n",
279 load_inst->readPC(), load_index, load_inst->seqNum);
281 load_inst->lqIdx = load_index;
283 loadQueue.push_front(load_inst);
284 LQItHash[load_index] = loadQueue.begin();
289 template <class Impl>
291 OzoneLWLSQ<Impl>::insertStore(DynInstPtr &store_inst)
293 // Make sure it is not full before inserting an instruction.
294 assert(stores - storesToWB < SQEntries);
296 assert(!SQIndices.empty());
297 int store_index = SQIndices.front();
300 DPRINTF(OzoneLSQ, "Inserting store PC %#x, idx:%i [sn:%lli]\n",
301 store_inst->readPC(), store_index, store_inst->seqNum);
303 store_inst->sqIdx = store_index;
304 SQEntry entry(store_inst);
305 if (loadQueue.empty()) {
306 entry.lqIt = loadQueue.end();
308 entry.lqIt = loadQueue.begin();
310 storeQueue.push_front(entry);
312 SQItHash[store_index] = storeQueue.begin();
317 template <class Impl>
318 typename Impl::DynInstPtr
319 OzoneLWLSQ<Impl>::getMemDepViolator()
321 DynInstPtr temp = memDepViolator;
323 memDepViolator = NULL;
328 template <class Impl>
330 OzoneLWLSQ<Impl>::numFreeEntries()
332 unsigned free_lq_entries = LQEntries - loads;
333 unsigned free_sq_entries = SQEntries - (stores + storesInFlight);
335 // Both the LQ and SQ entries have an extra dummy entry to differentiate
336 // empty/full conditions. Subtract 1 from the free entries.
337 if (free_lq_entries < free_sq_entries) {
338 return free_lq_entries - 1;
340 return free_sq_entries - 1;
344 template <class Impl>
346 OzoneLWLSQ<Impl>::numLoadsReady()
349 LQIt lq_it = loadQueue.begin();
350 LQIt end_it = loadQueue.end();
352 while (lq_it != end_it) {
353 if ((*lq_it)->readyToIssue()) {
361 template <class Impl>
363 OzoneLWLSQ<Impl>::executeLoad(DynInstPtr &inst)
365 // Execute a specific load.
366 Fault load_fault = NoFault;
368 DPRINTF(OzoneLSQ, "Executing load PC %#x, [sn:%lli]\n",
369 inst->readPC(),inst->seqNum);
371 // Make sure it's really in the list.
372 // Normally it should always be in the list. However,
373 /* due to a syscall it may not be the list.
377 if (i == loadTail && !find(inst)) {
378 assert(0 && "Load not in the queue!");
379 } else if (loadQueue[i] == inst) {
384 if (i >= LQEntries) {
390 load_fault = inst->initiateAcc();
392 // Might want to make sure that I'm not overwriting a previously faulting
393 // instruction that hasn't been checked yet.
394 // Actually probably want the oldest faulting load
395 if (load_fault != NoFault) {
396 DPRINTF(OzoneLSQ, "Load [sn:%lli] has a fault\n", inst->seqNum);
397 if (!(inst->req->isUncacheable() && !inst->isAtCommit())) {
400 // Maybe just set it as can commit here, although that might cause
401 // some other problems with sending traps to the ROB too quickly.
402 be->instToCommit(inst);
403 // iewStage->activityThisCycle();
409 template <class Impl>
411 OzoneLWLSQ<Impl>::executeStore(DynInstPtr &store_inst)
413 // Make sure that a store exists.
416 int store_idx = store_inst->sqIdx;
417 SQHashIt sq_hash_it = SQItHash.find(store_idx);
418 assert(sq_hash_it != SQItHash.end());
419 DPRINTF(OzoneLSQ, "Executing store PC %#x [sn:%lli]\n",
420 store_inst->readPC(), store_inst->seqNum);
422 SQIt sq_it = (*sq_hash_it).second;
424 Fault store_fault = store_inst->initiateAcc();
426 // Store size should now be available. Use it to get proper offset for
428 int size = (*sq_it).size;
431 DPRINTF(OzoneLSQ,"Fault on Store PC %#x, [sn:%lli],Size = 0\n",
432 store_inst->readPC(),store_inst->seqNum);
437 assert(store_fault == NoFault);
439 if (!storeFaultInst) {
440 if (store_fault != NoFault) {
441 panic("Fault in a store instruction!");
442 storeFaultInst = store_inst;
443 } else if (store_inst->isStoreConditional()) {
444 // Store conditionals need to set themselves as able to
445 // writeback if we haven't had a fault by here.
446 (*sq_it).canWB = true;
449 DPRINTF(OzoneLSQ, "Nonspeculative store! storesToWB:%i\n",
454 LQIt lq_it = --(loadQueue.end());
456 if (!memDepViolator) {
457 while (lq_it != loadQueue.end()) {
458 if ((*lq_it)->seqNum < store_inst->seqNum) {
462 // Actually should only check loads that have actually executed
463 // Might be safe because effAddr is set to InvalAddr when the
464 // dyn inst is created.
466 // Must actually check all addrs in the proper size range
467 // Which is more correct than needs to be. What if for now we just
468 // assume all loads are quad-word loads, and do the addr based
470 // @todo: Fix this, magic number being used here
471 if (((*lq_it)->effAddr >> 8) ==
472 (store_inst->effAddr >> 8)) {
473 // A load incorrectly passed this store. Squash and refetch.
474 // For now return a fault to show that it was unsuccessful.
475 memDepViolator = (*lq_it);
476 ++lsqMemOrderViolation;
478 return TheISA::genMachineCheckFault();
484 // If we've reached this point, there was no violation.
485 memDepViolator = NULL;
491 template <class Impl>
493 OzoneLWLSQ<Impl>::commitLoad()
495 assert(!loadQueue.empty());
497 DPRINTF(OzoneLSQ, "[sn:%lli] Committing head load instruction, PC %#x\n",
498 loadQueue.back()->seqNum, loadQueue.back()->readPC());
500 LQIndices.push(loadQueue.back()->lqIdx);
501 LQItHash.erase(loadQueue.back()->lqIdx);
503 loadQueue.pop_back();
508 template <class Impl>
510 OzoneLWLSQ<Impl>::commitLoads(InstSeqNum &youngest_inst)
512 assert(loads == 0 || !loadQueue.empty());
515 loadQueue.back()->seqNum <= youngest_inst) {
520 template <class Impl>
522 OzoneLWLSQ<Impl>::commitStores(InstSeqNum &youngest_inst)
524 assert(stores == 0 || !storeQueue.empty());
526 SQIt sq_it = --(storeQueue.end());
527 while (!storeQueue.empty() && sq_it != storeQueue.end()) {
528 assert((*sq_it).inst);
529 if (!(*sq_it).canWB) {
530 if ((*sq_it).inst->seqNum > youngest_inst) {
535 DPRINTF(OzoneLSQ, "Marking store as able to write back, PC "
536 "%#x [sn:%lli], storesToWB:%i\n",
537 (*sq_it).inst->readPC(),
538 (*sq_it).inst->seqNum,
541 (*sq_it).canWB = true;
548 template <class Impl>
550 OzoneLWLSQ<Impl>::writebackStores()
552 SQIt sq_it = --(storeQueue.end());
553 while (storesToWB > 0 &&
554 sq_it != storeQueue.end() &&
557 usedPorts < cachePorts) {
559 if (isStoreBlocked) {
560 DPRINTF(OzoneLSQ, "Unable to write back any more stores, cache"
565 DynInstPtr inst = (*sq_it).inst;
567 if ((*sq_it).size == 0 && !(*sq_it).completed) {
569 removeStore(inst->sqIdx);
574 if (inst->isDataPrefetch() || (*sq_it).committed) {
581 assert((*sq_it).req);
582 assert(!(*sq_it).committed);
584 Request *req = (*sq_it).req;
585 (*sq_it).committed = true;
587 assert(!inst->memData);
588 inst->memData = new uint8_t[64];
589 memcpy(inst->memData, (uint8_t *)&(*sq_it).data,
592 PacketPtr data_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
593 data_pkt->dataStatic(inst->memData);
595 LSQSenderState *state = new LSQSenderState;
596 state->isLoad = false;
597 state->idx = inst->sqIdx;
599 data_pkt->senderState = state;
601 DPRINTF(OzoneLSQ, "D-Cache: Writing back store PC:%#x "
602 "to Addr:%#x, data:%#x [sn:%lli]\n",
603 (*sq_it).inst->readPC(),
604 req->getPaddr(), *(inst->memData),
607 // @todo: Remove this SC hack once the memory system handles it.
608 if (req->isLocked()) {
609 if (req->isUncacheable()) {
616 // Hack: Instantly complete this store.
617 completeDataAccess(data_pkt);
623 // Non-store conditionals do not need a writeback.
627 if (!dcachePort.sendTiming(data_pkt)) {
628 // Need to handle becoming blocked on a store.
629 isStoreBlocked = true;
630 assert(retryPkt == NULL);
633 storePostSend(data_pkt, inst);
637 DPRINTF(OzoneLSQ, "D-Cache: Writing back store idx:%i PC:%#x "
638 "to Addr:%#x, data:%#x [sn:%lli]\n",
639 inst->sqIdx,inst->readPC(),
640 req->paddr, *(req->data),
642 DPRINTF(OzoneLSQ, "StoresInFlight: %i\n",
645 if (dcacheInterface) {
646 assert(!req->completionEvent);
647 StoreCompletionEvent *store_event = new
648 StoreCompletionEvent(inst, be, NULL, this);
649 req->completionEvent = store_event;
651 MemAccessResult result = dcacheInterface->access(req);
654 inst->seqNum == stallingStoreIsn) {
655 DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
657 stallingStoreIsn, (*stallingLoad)->seqNum);
659 stallingStoreIsn = 0;
660 be->replayMemInst((*stallingLoad));
663 if (result != MA_HIT && dcacheInterface->doEvents()) {
664 store_event->miss = true;
665 typename BackEnd::LdWritebackEvent *wb = NULL;
666 if (req->isLocked()) {
667 wb = new typename BackEnd::LdWritebackEvent(inst,
669 store_event->wbEvent = wb;
672 DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
674 // DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
677 be->addDcacheMiss(inst);
679 lastDcacheStall = curTick;
681 _status = DcacheMissStall;
683 // Increment stat here or something
687 DPRINTF(OzoneLSQ,"D-Cache: Write Hit on idx:%i !\n",
690 // DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
693 if (req->isLocked()) {
694 // Stx_C does not generate a system port
695 // transaction in the 21264, but that might be
696 // hard to accomplish in this model.
698 typename BackEnd::LdWritebackEvent *wb =
699 new typename BackEnd::LdWritebackEvent(inst,
701 store_event->wbEvent = wb;
706 // removeStore(inst->sqIdx);
708 panic("Must HAVE DCACHE!!!!!\n");
713 // Not sure this should set it to 0.
716 assert(stores >= 0 && storesToWB >= 0);
719 template <class Impl>
721 OzoneLWLSQ<Impl>::squash(const InstSeqNum &squashed_num)
723 DPRINTF(OzoneLSQ, "Squashing until [sn:%lli]!"
724 "(Loads:%i Stores:%i)\n",squashed_num,loads,stores+storesInFlight);
727 LQIt lq_it = loadQueue.begin();
729 while (loads != 0 && (*lq_it)->seqNum > squashed_num) {
730 assert(!loadQueue.empty());
731 // Clear the smart pointer to make sure it is decremented.
732 DPRINTF(OzoneLSQ,"Load Instruction PC %#x squashed, "
737 if (isStalled() && lq_it == stallingLoad) {
739 stallingStoreIsn = 0;
746 LQHashIt lq_hash_it = LQItHash.find((*lq_it)->lqIdx);
747 assert(lq_hash_it != LQItHash.end());
748 LQItHash.erase(lq_hash_it);
749 LQIndices.push((*lq_it)->lqIdx);
750 loadQueue.erase(lq_it++);
754 if (squashed_num < blockedLoadSeqNum) {
755 isLoadBlocked = false;
756 loadBlockedHandled = false;
757 blockedLoadSeqNum = 0;
761 SQIt sq_it = storeQueue.begin();
763 while (stores != 0 && (*sq_it).inst->seqNum > squashed_num) {
764 assert(!storeQueue.empty());
766 if ((*sq_it).canWB) {
770 // Clear the smart pointer to make sure it is decremented.
771 DPRINTF(OzoneLSQ,"Store Instruction PC %#x idx:%i squashed [sn:%lli]\n",
772 (*sq_it).inst->readPC(), (*sq_it).inst->sqIdx,
773 (*sq_it).inst->seqNum);
775 // I don't think this can happen. It should have been cleared by the
778 (*sq_it).inst->seqNum == stallingStoreIsn) {
779 panic("Is stalled should have been cleared by stalling load!\n");
781 stallingStoreIsn = 0;
784 SQHashIt sq_hash_it = SQItHash.find((*sq_it).inst->sqIdx);
785 assert(sq_hash_it != SQItHash.end());
786 SQItHash.erase(sq_hash_it);
787 SQIndices.push((*sq_it).inst->sqIdx);
788 (*sq_it).inst = NULL;
792 storeQueue.erase(sq_it++);
796 template <class Impl>
798 OzoneLWLSQ<Impl>::dumpInsts()
800 cprintf("Load store queue: Dumping instructions.\n");
801 cprintf("Load queue size: %i\n", loads);
802 cprintf("Load queue: ");
804 LQIt lq_it = --(loadQueue.end());
806 while (lq_it != loadQueue.end() && (*lq_it)) {
807 cprintf("[sn:%lli] %#x ", (*lq_it)->seqNum,
813 cprintf("\nStore queue size: %i\n", stores);
814 cprintf("Store queue: ");
816 SQIt sq_it = --(storeQueue.end());
818 while (sq_it != storeQueue.end() && (*sq_it).inst) {
819 cprintf("[sn:%lli]\nPC:%#x\nSize:%i\nCommitted:%i\nCompleted:%i\ncanWB:%i\n",
820 (*sq_it).inst->seqNum,
821 (*sq_it).inst->readPC(),
833 template <class Impl>
835 OzoneLWLSQ<Impl>::storePostSend(PacketPtr pkt, DynInstPtr &inst)
838 inst->seqNum == stallingStoreIsn) {
839 DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
841 stallingStoreIsn, (*stallingLoad)->seqNum);
843 stallingStoreIsn = 0;
844 be->replayMemInst((*stallingLoad));
847 if (!inst->isStoreConditional()) {
848 // The store is basically completed at this time. This
849 // only works so long as the checker doesn't try to
850 // verify the value in memory for stores.
851 inst->setCompleted();
854 cpu->checker->verify(inst);
859 if (pkt->result != Packet::Success) {
860 DPRINTF(OzoneLSQ,"D-Cache Write Miss!\n");
862 DPRINTF(Activity, "Active st accessing mem miss [sn:%lli]\n",
865 //mshrSeqNums.push_back(storeQueue[storeWBIdx].inst->seqNum);
867 //DPRINTF(OzoneLWLSQ, "Added MSHR. count = %i\n",mshrSeqNums.size());
869 // @todo: Increment stat here.
871 DPRINTF(OzoneLSQ,"D-Cache: Write Hit!\n");
873 DPRINTF(Activity, "Active st accessing mem hit [sn:%lli]\n",
878 template <class Impl>
880 OzoneLWLSQ<Impl>::writeback(DynInstPtr &inst, PacketPtr pkt)
882 // Squashed instructions do not need to complete their access.
883 if (inst->isSquashed()) {
884 assert(!inst->isStore());
888 if (!inst->isExecuted()) {
891 // Complete access to copy data to proper place.
892 inst->completeAcc(pkt);
895 // Need to insert instruction into queue to commit
896 be->instToCommit(inst);
899 template <class Impl>
901 OzoneLWLSQ<Impl>::removeStore(int store_idx)
903 SQHashIt sq_hash_it = SQItHash.find(store_idx);
904 assert(sq_hash_it != SQItHash.end());
905 SQIt sq_it = (*sq_hash_it).second;
907 assert((*sq_it).inst);
908 (*sq_it).completed = true;
909 DynInstPtr inst = (*sq_it).inst;
912 inst->seqNum == stallingStoreIsn) {
913 DPRINTF(OzoneLSQ, "Unstalling, stalling store [sn:%lli] "
915 stallingStoreIsn, (*stallingLoad)->seqNum);
917 stallingStoreIsn = 0;
918 be->replayMemInst((*stallingLoad));
921 DPRINTF(OzoneLSQ, "Completing store idx:%i [sn:%lli], storesToWB:%i\n",
922 inst->sqIdx, inst->seqNum, storesToWB);
924 assert(!storeQueue.empty());
925 SQItHash.erase(sq_hash_it);
926 SQIndices.push(inst->sqIdx);
927 storeQueue.erase(sq_it);
930 template <class Impl>
932 OzoneLWLSQ<Impl>::completeStore(DynInstPtr &inst)
937 inst->setCompleted();
940 cpu->checker->verify(inst);
945 template <class Impl>
947 OzoneLWLSQ<Impl>::recvRetry()
949 panic("Unimplemented!");
952 template <class Impl>
954 OzoneLWLSQ<Impl>::switchOut()
956 assert(storesToWB == 0);
959 // Clear the queue to free up resources
961 assert(storeQueue.empty());
963 assert(loadQueue.empty());
964 assert(storesInFlight == 0);
967 loads = stores = storesToWB = storesInFlight = 0;
970 template <class Impl>
972 OzoneLWLSQ<Impl>::takeOverFrom(ThreadContext *old_tc)
974 // Clear out any old state. May be redundant if this is the first time
975 // the CPU is being used.
977 isLoadBlocked = false;
978 loadBlockedHandled = false;
981 // Could do simple checks here to see if indices are on twice
982 while (!LQIndices.empty())
984 while (!SQIndices.empty())
987 for (int i = 0; i < LQEntries * 2; i++) {
994 loadFaultInst = storeFaultInst = memDepViolator = NULL;
996 blockedLoadSeqNum = 0;