src/cpu/ozone/null_predictor.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_OZONE_NULL_PREDICTOR_HH__
  32 #define __CPU_OZONE_NULL_PREDICTOR_HH__
  33
  34 #include "cpu/inst_seq.hh"
  35 #include "sim/host.hh"
  36
  37 template <class Impl>
  38 class NullPredictor
  39 {
  40   public:
  41     typedef typename Impl::Params Params;
  42     typedef typename Impl::DynInstPtr DynInstPtr;
  43
  44     NullPredictor(Params *p) { }
  45
  46     struct BPredInfo {
  47         BPredInfo()
  48             : PC(0), nextPC(0)
  49         { }
  50
  51         BPredInfo(const Addr &pc, const Addr &next_pc)
  52             : PC(pc), nextPC(next_pc)
  53         { }
  54
  55         Addr PC;
  56         Addr nextPC;
  57     };
  58
  59     BPredInfo lookup(Addr &PC) { return BPredInfo(PC, PC+4); }
  60
  61     void undo(BPredInfo &bp_info) { return; }
  62
  63     /**
  64      * Predicts whether or not the instruction is a taken branch, and the
  65      * target of the branch if it is taken.
  66      * @param inst The branch instruction.
  67      * @param PC The predicted PC is passed back through this parameter.
  68      * @param tid The thread id.
  69      * @return Returns if the branch is taken or not.
  70      */
  71     bool predict(DynInstPtr &inst, Addr &PC, unsigned tid)
  72     { return false; }
  73
  74     /**
  75      * Tells the branch predictor to commit any updates until the given
  76      * sequence number.
  77      * @param done_sn The sequence number to commit any older updates up until.
  78      * @param tid The thread id.
  79      */
  80     void update(const InstSeqNum &done_sn, unsigned tid) { }
  81
  82     /**
  83      * Squashes all outstanding updates until a given sequence number.
  84      * @param squashed_sn The sequence number to squash any younger updates up
  85      * until.
  86      * @param tid The thread id.
  87      */
  88     void squash(const InstSeqNum &squashed_sn, unsigned tid) { }
  89
  90     /**
  91      * Squashes all outstanding updates until a given sequence number, and
  92      * corrects that sn's update with the proper address and taken/not taken.
  93      * @param squashed_sn The sequence number to squash any younger updates up
  94      * until.
  95      * @param corr_target The correct branch target.
  96      * @param actually_taken The correct branch direction.
  97      * @param tid The thread id.
  98      */
  99     void squash(const InstSeqNum &squashed_sn, const Addr &corr_target,
 100                 bool actually_taken, unsigned tid)
 101     { }
 102
 103 };
 104
 105 #endif // __CPU_OZONE_NULL_PREDICTOR_HH__