src/cpu/ozone/thread_state.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_OZONE_THREAD_STATE_HH__
  32 #define __CPU_OZONE_THREAD_STATE_HH__
  33
  34 #include "arch/faults.hh"
  35 #include "arch/types.hh"
  36 #include "arch/regfile.hh"
  37 #include "base/callback.hh"
  38 #include "base/output.hh"
  39 #include "cpu/thread_context.hh"
  40 #include "cpu/thread_state.hh"
  41 #include "sim/process.hh"
  42 #include "sim/sim_exit.hh"
  43
  44 class Event;
  45 //class Process;
  46
  47 #if FULL_SYSTEM
  48 class EndQuiesceEvent;
  49 class FunctionProfile;
  50 class ProfileNode;
  51 #else
  52 class Process;
  53 class FunctionalMemory;
  54 #endif
  55
  56 // Maybe this ozone thread state should only really have committed state?
  57 // I need to think about why I'm using this and what it's useful for.  Clearly
  58 // has benefits for SMT; basically serves same use as SimpleThread.
  59 // Makes the ExecContext proxy easier.  Gives organization/central access point
  60 // to state of a thread that can be accessed normally (i.e. not in-flight
  61 // stuff within a OoO processor).  Does this need an TC proxy within it?
  62 template <class Impl>
  63 struct OzoneThreadState : public ThreadState {
  64     typedef typename ThreadContext::Status Status;
  65     typedef typename Impl::CPUType CPUType;
  66     typedef TheISA::MiscReg MiscReg;
  67
  68 #if FULL_SYSTEM
  69     OzoneThreadState(CPUType *_cpu, int _thread_num)
  70         : ThreadState(-1, _thread_num),
  71           cpu(_cpu), intrflag(0), inSyscall(0), trapPending(0)
  72     {
  73         if (cpu->params->profile) {
  74             profile = new FunctionProfile(cpu->params->system->kernelSymtab);
  75             Callback *cb =
  76                 new MakeCallback<OzoneThreadState,
  77                 &OzoneThreadState::dumpFuncProfile>(this);
  78             registerExitCallback(cb);
  79         }
  80
  81         // let's fill with a dummy node for now so we don't get a segfault
  82         // on the first cycle when there's no node available.
  83         static ProfileNode dummyNode;
  84         profileNode = &dummyNode;
  85         profilePC = 3;
  86         miscRegFile.clear();
  87     }
  88 #else
  89     OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process,
  90                      int _asid, MemObject *mem)
  91         : ThreadState(-1, _thread_num, _process, _asid, mem),
  92           cpu(_cpu), inSyscall(0), trapPending(0)
  93     {
  94         miscRegFile.clear();
  95     }
  96 #endif
  97
  98     RenameTable<Impl> renameTable;
  99
 100     Addr PC;
 101
 102     Addr nextPC;
 103
 104     TheISA::MiscRegFile miscRegFile;
 105
 106     int intrflag;
 107
 108     typename Impl::CPUType *cpu;
 109
 110     bool inSyscall;
 111
 112     bool trapPending;
 113
 114     ThreadContext *tc;
 115
 116     ThreadContext *getTC() { return tc; }
 117
 118     MiscReg readMiscReg(int misc_reg)
 119     {
 120         return miscRegFile.readReg(misc_reg);
 121     }
 122
 123     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
 124     {
 125         return miscRegFile.readRegWithEffect(misc_reg, fault, tc);
 126     }
 127
 128     Fault setMiscReg(int misc_reg, const MiscReg &val)
 129     {
 130         return miscRegFile.setReg(misc_reg, val);
 131     }
 132
 133     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 134     {
 135         return miscRegFile.setRegWithEffect(misc_reg, val, tc);
 136     }
 137
 138     uint64_t readPC()
 139     { return PC; }
 140
 141     void setPC(uint64_t val)
 142     { PC = val; }
 143
 144     uint64_t readNextPC()
 145     { return nextPC; }
 146
 147     void setNextPC(uint64_t val)
 148     { nextPC = val; }
 149
 150 #if FULL_SYSTEM
 151     void dumpFuncProfile()
 152     {
 153         std::ostream *os = simout.create(csprintf("profile.%s.dat", cpu->name()));
 154         profile->dump(xcProxy, *os);
 155     }
 156 #endif
 157 };
 158
 159 #endif // __CPU_OZONE_THREAD_STATE_HH__