src/cpu/ozone/thread_state.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_OZONE_THREAD_STATE_HH__
  32 #define __CPU_OZONE_THREAD_STATE_HH__
  33
  34 #include "arch/faults.hh"
  35 #include "arch/isa_traits.hh"
  36 #include "cpu/thread_context.hh"
  37 #include "cpu/thread_state.hh"
  38 #include "sim/process.hh"
  39
  40 class Event;
  41 //class Process;
  42
  43 #if FULL_SYSTEM
  44 class EndQuiesceEvent;
  45 class FunctionProfile;
  46 class ProfileNode;
  47 #else
  48 class Process;
  49 class FunctionalMemory;
  50 #endif
  51
  52 // Maybe this ozone thread state should only really have committed state?
  53 // I need to think about why I'm using this and what it's useful for.  Clearly
  54 // has benefits for SMT; basically serves same use as SimpleThread.
  55 // Makes the ExecContext proxy easier.  Gives organization/central access point
  56 // to state of a thread that can be accessed normally (i.e. not in-flight
  57 // stuff within a OoO processor).  Does this need an TC proxy within it?
  58 template <class Impl>
  59 struct OzoneThreadState : public ThreadState {
  60     typedef typename ThreadContext::Status Status;
  61     typedef typename Impl::CPUType CPUType;
  62     typedef TheISA::MiscReg MiscReg;
  63
  64 #if FULL_SYSTEM
  65     OzoneThreadState(CPUType *_cpu, int _thread_num)
  66         : ThreadState(-1, _thread_num),
  67           intrflag(0), inSyscall(0), trapPending(0)
  68     {
  69         miscRegFile.clear();
  70     }
  71 #else
  72     OzoneThreadState(CPUType *_cpu, int _thread_num, Process *_process,
  73                      int _asid, MemObject *mem)
  74         : ThreadState(-1, _thread_num, _process, _asid, mem),
  75           cpu(_cpu), inSyscall(0), trapPending(0)
  76     {
  77         miscRegFile.clear();
  78     }
  79 #endif
  80
  81     RenameTable<Impl> renameTable;
  82
  83     Addr PC;
  84
  85     Addr nextPC;
  86
  87     TheISA::MiscRegFile miscRegFile;
  88
  89     int intrflag;
  90
  91     typename Impl::CPUType *cpu;
  92
  93     bool inSyscall;
  94
  95     bool trapPending;
  96
  97     ThreadContext *tc;
  98
  99     ThreadContext *getTC() { return tc; }
 100
 101     MiscReg readMiscReg(int misc_reg)
 102     {
 103         return miscRegFile.readReg(misc_reg);
 104     }
 105
 106     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
 107     {
 108         return miscRegFile.readRegWithEffect(misc_reg, fault, tc);
 109     }
 110
 111     Fault setMiscReg(int misc_reg, const MiscReg &val)
 112     {
 113         return miscRegFile.setReg(misc_reg, val);
 114     }
 115
 116     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 117     {
 118         return miscRegFile.setRegWithEffect(misc_reg, val, tc);
 119     }
 120
 121     uint64_t readPC()
 122     { return PC; }
 123
 124     void setPC(uint64_t val)
 125     { PC = val; }
 126
 127     uint64_t readNextPC()
 128     { return nextPC; }
 129
 130     void setNextPC(uint64_t val)
 131     { nextPC = val; }
 132 };
 133
 134 #endif // __CPU_OZONE_THREAD_STATE_HH__