src/cpu/ozone/thread_state.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #ifndef __CPU_OZONE_THREAD_STATE_HH__
  32 #define __CPU_OZONE_THREAD_STATE_HH__
  33
  34 #include "arch/faults.hh"
  35 #include "arch/isa_traits.hh"
  36 #include "cpu/thread_context.hh"
  37 #include "cpu/thread_state.hh"
  38 #include "sim/process.hh"
  39
  40 class Event;
  41 //class Process;
  42
  43 #if FULL_SYSTEM
  44 class EndQuiesceEvent;
  45 class FunctionProfile;
  46 class ProfileNode;
  47 #else
  48 class Process;
  49 class FunctionalMemory;
  50 #endif
  51
  52 // Maybe this ozone thread state should only really have committed state?
  53 // I need to think about why I'm using this and what it's useful for.  Clearly
  54 // has benefits for SMT; basically serves same use as SimpleThread.
  55 // Makes the ExecContext proxy easier.  Gives organization/central access point
  56 // to state of a thread that can be accessed normally (i.e. not in-flight
  57 // stuff within a OoO processor).  Does this need an TC proxy within it?
  58 template <class Impl>
  59 struct OzoneThreadState : public ThreadState {
  60     typedef typename ThreadContext::Status Status;
  61     typedef typename Impl::FullCPU FullCPU;
  62     typedef TheISA::MiscReg MiscReg;
  63
  64 #if FULL_SYSTEM
  65     OzoneThreadState(FullCPU *_cpu, int _thread_num)
  66         : ThreadState(-1, _thread_num),
  67           inSyscall(0), trapPending(0)
  68     {
  69         memset(&regs, 0, sizeof(TheISA::RegFile));
  70     }
  71 #else
  72     OzoneThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid)
  73         : ThreadState(-1, _thread_num, NULL, _process, _asid),
  74           cpu(_cpu), inSyscall(0), trapPending(0)
  75     {
  76         memset(&regs, 0, sizeof(TheISA::RegFile));
  77     }
  78
  79     OzoneThreadState(FullCPU *_cpu, int _thread_num,
  80                      int _asid)
  81         : ThreadState(-1, _thread_num, NULL, NULL, _asid),
  82           cpu(_cpu), inSyscall(0), trapPending(0)
  83     {
  84         memset(&regs, 0, sizeof(TheISA::RegFile));
  85     }
  86 #endif
  87
  88     RenameTable<Impl> renameTable;
  89
  90     Addr PC;
  91
  92     Addr nextPC;
  93
  94     TheISA::RegFile regs;
  95
  96     typename Impl::FullCPU *cpu;
  97
  98     bool inSyscall;
  99
 100     bool trapPending;
 101
 102     ThreadContext *tc;
 103
 104     ThreadContext *getTC() { return tc; }
 105
 106 #if !FULL_SYSTEM
 107     Fault translateInstReq(Request *req)
 108     {
 109         return process->pTable->translate(req);
 110     }
 111     Fault translateDataReadReq(Request *req)
 112     {
 113         return process->pTable->translate(req);
 114     }
 115     Fault translateDataWriteReq(Request *req)
 116     {
 117         return process->pTable->translate(req);
 118     }
 119 #else
 120     Fault translateInstReq(Request *req)
 121     {
 122         return cpu->itb->translate(req);
 123     }
 124
 125     Fault translateDataReadReq(Request *req)
 126     {
 127         return cpu->dtb->translate(req, false);
 128     }
 129
 130     Fault translateDataWriteReq(Request *req)
 131     {
 132         return cpu->dtb->translate(req, true);
 133     }
 134 #endif
 135
 136     MiscReg readMiscReg(int misc_reg)
 137     {
 138         return regs.readMiscReg(misc_reg);
 139     }
 140
 141     MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
 142     {
 143         return regs.readMiscRegWithEffect(misc_reg, fault, tc);
 144     }
 145
 146     Fault setMiscReg(int misc_reg, const MiscReg &val)
 147     {
 148         return regs.setMiscReg(misc_reg, val);
 149     }
 150
 151     Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
 152     {
 153         return regs.setMiscRegWithEffect(misc_reg, val, tc);
 154     }
 155
 156     uint64_t readPC()
 157     { return PC; }
 158
 159     void setPC(uint64_t val)
 160     { PC = val; }
 161
 162     uint64_t readNextPC()
 163     { return nextPC; }
 164
 165     void setNextPC(uint64_t val)
 166     { nextPC = val; }
 167 };
 168
 169 #endif // __CPU_OZONE_THREAD_STATE_HH__