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31 #ifndef __CPU_OZONE_THREAD_STATE_HH__
32 #define __CPU_OZONE_THREAD_STATE_HH__
34 #include "arch/faults.hh"
35 #include "arch/isa_traits.hh"
36 #include "cpu/thread_context.hh"
37 #include "cpu/thread_state.hh"
38 #include "sim/process.hh"
44 class EndQuiesceEvent;
45 class FunctionProfile;
49 class FunctionalMemory;
52 // Maybe this ozone thread state should only really have committed state?
53 // I need to think about why I'm using this and what it's useful for. Clearly
54 // has benefits for SMT; basically serves same use as SimpleThread.
55 // Makes the ExecContext proxy easier. Gives organization/central access point
56 // to state of a thread that can be accessed normally (i.e. not in-flight
57 // stuff within a OoO processor). Does this need an TC proxy within it?
59 struct OzoneThreadState : public ThreadState {
60 typedef typename ThreadContext::Status Status;
61 typedef typename Impl::FullCPU FullCPU;
62 typedef TheISA::MiscReg MiscReg;
65 OzoneThreadState(FullCPU *_cpu, int _thread_num)
66 : ThreadState(-1, _thread_num),
67 inSyscall(0), trapPending(0)
69 memset(®s, 0, sizeof(TheISA::RegFile));
72 OzoneThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid)
73 : ThreadState(-1, _thread_num, NULL, _process, _asid),
74 cpu(_cpu), inSyscall(0), trapPending(0)
76 memset(®s, 0, sizeof(TheISA::RegFile));
79 OzoneThreadState(FullCPU *_cpu, int _thread_num,
81 : ThreadState(-1, _thread_num, NULL, NULL, _asid),
82 cpu(_cpu), inSyscall(0), trapPending(0)
84 memset(®s, 0, sizeof(TheISA::RegFile));
88 RenameTable<Impl> renameTable;
96 typename Impl::FullCPU *cpu;
104 ThreadContext *getTC() { return tc; }
107 Fault translateInstReq(Request *req)
109 return process->pTable->translate(req);
111 Fault translateDataReadReq(Request *req)
113 return process->pTable->translate(req);
115 Fault translateDataWriteReq(Request *req)
117 return process->pTable->translate(req);
120 Fault translateInstReq(Request *req)
122 return cpu->itb->translate(req);
125 Fault translateDataReadReq(Request *req)
127 return cpu->dtb->translate(req, false);
130 Fault translateDataWriteReq(Request *req)
132 return cpu->dtb->translate(req, true);
136 MiscReg readMiscReg(int misc_reg)
138 return regs.readMiscReg(misc_reg);
141 MiscReg readMiscRegWithEffect(int misc_reg, Fault &fault)
143 return regs.readMiscRegWithEffect(misc_reg, fault, tc);
146 Fault setMiscReg(int misc_reg, const MiscReg &val)
148 return regs.setMiscReg(misc_reg, val);
151 Fault setMiscRegWithEffect(int misc_reg, const MiscReg &val)
153 return regs.setMiscRegWithEffect(misc_reg, val, tc);
159 void setPC(uint64_t val)
162 uint64_t readNextPC()
165 void setNextPC(uint64_t val)
169 #endif // __CPU_OZONE_THREAD_STATE_HH__