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4 * Copyright (c) 2012 Mark D. Hill and David A. Wood
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45 #include "cpu/pred/bpred_unit.hh"
49 #include "arch/isa_traits.hh"
50 #include "arch/types.hh"
51 #include "arch/utility.hh"
52 #include "base/trace.hh"
53 #include "config/the_isa.hh"
54 #include "debug/Branch.hh"
56 BPredUnit::BPredUnit(const Params
*params
)
58 numThreads(params
->numThreads
),
60 BTB(params
->BTBEntries
,
65 useIndirect(params
->useIndirect
),
66 iPred(params
->indirectHashGHR
,
67 params
->indirectHashTargets
,
70 params
->indirectTagSize
,
71 params
->indirectPathLength
,
74 instShiftAmt(params
->instShiftAmt
)
77 r
.init(params
->RASSize
);
83 SimObject::regStats();
86 .name(name() + ".lookups")
87 .desc("Number of BP lookups")
91 .name(name() + ".condPredicted")
92 .desc("Number of conditional branches predicted")
96 .name(name() + ".condIncorrect")
97 .desc("Number of conditional branches incorrect")
101 .name(name() + ".BTBLookups")
102 .desc("Number of BTB lookups")
106 .name(name() + ".BTBHits")
107 .desc("Number of BTB hits")
111 .name(name() + ".BTBCorrect")
112 .desc("Number of correct BTB predictions (this stat may not "
117 .name(name() + ".BTBHitPct")
118 .desc("BTB Hit Percentage")
120 BTBHitPct
= (BTBHits
/ BTBLookups
) * 100;
123 .name(name() + ".usedRAS")
124 .desc("Number of times the RAS was used to get a target.")
128 .name(name() + ".RASInCorrect")
129 .desc("Number of incorrect RAS predictions.")
133 .name(name() + ".indirectLookups")
134 .desc("Number of indirect predictor lookups.")
138 .name(name() + ".indirectHits")
139 .desc("Number of indirect target hits.")
143 .name(name() + ".indirectMisses")
144 .desc("Number of indirect misses.")
148 .name(name() + "indirectMispredicted")
149 .desc("Number of mispredicted indirect branches.")
155 BPredUnit::pmuProbePoint(const char *name
)
157 ProbePoints::PMUUPtr ptr
;
158 ptr
.reset(new ProbePoints::PMU(getProbeManager(), name
));
164 BPredUnit::regProbePoints()
166 ppBranches
= pmuProbePoint("Branches");
167 ppMisses
= pmuProbePoint("Misses");
171 BPredUnit::drainSanityCheck() const
173 // We shouldn't have any outstanding requests when we resume from
175 for (const auto& ph M5_VAR_USED
: predHist
)
180 BPredUnit::predict(const StaticInstPtr
&inst
, const InstSeqNum
&seqNum
,
181 TheISA::PCState
&pc
, ThreadID tid
)
183 // See if branch predictor predicts taken.
184 // If so, get its target addr either from the BTB or the RAS.
185 // Save off record of branch stuff so the RAS can be fixed
186 // up once it's done.
188 bool pred_taken
= false;
189 TheISA::PCState target
= pc
;
192 ppBranches
->notify(1);
194 void *bp_history
= NULL
;
196 if (inst
->isUncondCtrl()) {
197 DPRINTF(Branch
, "[tid:%i]: Unconditional control.\n", tid
);
199 // Tell the BP there was an unconditional branch.
200 uncondBranch(tid
, pc
.instAddr(), bp_history
);
203 pred_taken
= lookup(tid
, pc
.instAddr(), bp_history
);
205 DPRINTF(Branch
, "[tid:%i]: [sn:%i] Branch predictor"
206 " predicted %i for PC %s\n", tid
, seqNum
, pred_taken
, pc
);
209 DPRINTF(Branch
, "[tid:%i]: [sn:%i] Creating prediction history "
210 "for PC %s\n", tid
, seqNum
, pc
);
212 PredictorHistory
predict_record(seqNum
, pc
.instAddr(),
213 pred_taken
, bp_history
, tid
);
215 // Now lookup in the BTB or RAS.
217 if (inst
->isReturn()) {
219 predict_record
.wasReturn
= true;
220 // If it's a function return call, then look up the address
222 TheISA::PCState rasTop
= RAS
[tid
].top();
223 target
= TheISA::buildRetPC(pc
, rasTop
);
225 // Record the top entry of the RAS, and its index.
226 predict_record
.usedRAS
= true;
227 predict_record
.RASIndex
= RAS
[tid
].topIdx();
228 predict_record
.RASTarget
= rasTop
;
232 DPRINTF(Branch
, "[tid:%i]: Instruction %s is a return, "
233 "RAS predicted target: %s, RAS index: %i.\n",
234 tid
, pc
, target
, predict_record
.RASIndex
);
238 if (inst
->isCall()) {
240 predict_record
.pushedRAS
= true;
242 // Record that it was a call so that the top RAS entry can
243 // be popped off if the speculation is incorrect.
244 predict_record
.wasCall
= true;
246 DPRINTF(Branch
, "[tid:%i]: Instruction %s was a "
247 "call, adding %s to the RAS index: %i.\n",
248 tid
, pc
, pc
, RAS
[tid
].topIdx());
251 if (inst
->isDirectCtrl() || !useIndirect
) {
252 // Check BTB on direct branches
253 if (BTB
.valid(pc
.instAddr(), tid
)) {
256 // If it's not a return, use the BTB to get target addr.
257 target
= BTB
.lookup(pc
.instAddr(), tid
);
259 DPRINTF(Branch
, "[tid:%i]: Instruction %s predicted"
260 " target is %s.\n", tid
, pc
, target
);
263 DPRINTF(Branch
, "[tid:%i]: BTB doesn't have a "
264 "valid entry.\n",tid
);
266 // The Direction of the branch predictor is altered
267 // because the BTB did not have an entry
268 // The predictor needs to be updated accordingly
269 if (!inst
->isCall() && !inst
->isReturn()) {
270 btbUpdate(tid
, pc
.instAddr(), bp_history
);
271 DPRINTF(Branch
, "[tid:%i]:[sn:%i] btbUpdate"
272 " called for %s\n", tid
, seqNum
, pc
);
273 } else if (inst
->isCall() && !inst
->isUncondCtrl()) {
275 predict_record
.pushedRAS
= false;
277 TheISA::advancePC(target
, inst
);
280 predict_record
.wasIndirect
= true;
282 //Consult indirect predictor on indirect control
283 if (iPred
.lookup(pc
.instAddr(), getGHR(tid
, bp_history
),
285 // Indirect predictor hit
287 DPRINTF(Branch
, "[tid:%i]: Instruction %s predicted "
288 "indirect target is %s.\n", tid
, pc
, target
);
292 DPRINTF(Branch
, "[tid:%i]: Instruction %s no indirect "
293 "target.\n", tid
, pc
);
294 if (!inst
->isCall() && !inst
->isReturn()) {
296 } else if (inst
->isCall() && !inst
->isUncondCtrl()) {
298 predict_record
.pushedRAS
= false;
300 TheISA::advancePC(target
, inst
);
302 iPred
.recordIndirect(pc
.instAddr(), target
.instAddr(), seqNum
,
307 if (inst
->isReturn()) {
308 predict_record
.wasReturn
= true;
310 TheISA::advancePC(target
, inst
);
315 predHist
[tid
].push_front(predict_record
);
317 DPRINTF(Branch
, "[tid:%i]: [sn:%i]: History entry added."
318 "predHist.size(): %i\n", tid
, seqNum
, predHist
[tid
].size());
324 BPredUnit::update(const InstSeqNum
&done_sn
, ThreadID tid
)
326 DPRINTF(Branch
, "[tid:%i]: Committing branches until "
327 "[sn:%lli].\n", tid
, done_sn
);
329 iPred
.commit(done_sn
, tid
);
330 while (!predHist
[tid
].empty() &&
331 predHist
[tid
].back().seqNum
<= done_sn
) {
332 // Update the branch predictor with the correct results.
333 update(tid
, predHist
[tid
].back().pc
,
334 predHist
[tid
].back().predTaken
,
335 predHist
[tid
].back().bpHistory
, false);
337 predHist
[tid
].pop_back();
342 BPredUnit::squash(const InstSeqNum
&squashed_sn
, ThreadID tid
)
344 History
&pred_hist
= predHist
[tid
];
346 iPred
.squash(squashed_sn
, tid
);
347 while (!pred_hist
.empty() &&
348 pred_hist
.front().seqNum
> squashed_sn
) {
349 if (pred_hist
.front().usedRAS
) {
350 DPRINTF(Branch
, "[tid:%i]: Restoring top of RAS to: %i,"
351 " target: %s.\n", tid
,
352 pred_hist
.front().RASIndex
, pred_hist
.front().RASTarget
);
354 RAS
[tid
].restore(pred_hist
.front().RASIndex
,
355 pred_hist
.front().RASTarget
);
356 } else if (pred_hist
.front().wasCall
&& pred_hist
.front().pushedRAS
) {
357 // Was a call but predicated false. Pop RAS here
358 DPRINTF(Branch
, "[tid: %i] Squashing"
359 " Call [sn:%i] PC: %s Popping RAS\n", tid
,
360 pred_hist
.front().seqNum
, pred_hist
.front().pc
);
364 // This call should delete the bpHistory.
365 squash(tid
, pred_hist
.front().bpHistory
);
367 DPRINTF(Branch
, "[tid:%i]: Removing history for [sn:%i] "
368 "PC %s.\n", tid
, pred_hist
.front().seqNum
,
369 pred_hist
.front().pc
);
371 pred_hist
.pop_front();
373 DPRINTF(Branch
, "[tid:%i]: predHist.size(): %i\n",
374 tid
, predHist
[tid
].size());
379 BPredUnit::squash(const InstSeqNum
&squashed_sn
,
380 const TheISA::PCState
&corrTarget
,
381 bool actually_taken
, ThreadID tid
)
383 // Now that we know that a branch was mispredicted, we need to undo
384 // all the branches that have been seen up until this branch and
385 // fix up everything.
386 // NOTE: This should be call conceivably in 2 scenarios:
387 // (1) After an branch is executed, it updates its status in the ROB
388 // The commit stage then checks the ROB update and sends a signal to
389 // the fetch stage to squash history after the mispredict
390 // (2) In the decode stage, you can find out early if a unconditional
391 // PC-relative, branch was predicted incorrectly. If so, a signal
392 // to the fetch stage is sent to squash history after the mispredict
394 History
&pred_hist
= predHist
[tid
];
399 DPRINTF(Branch
, "[tid:%i]: Squashing from sequence number %i, "
400 "setting target to %s.\n", tid
, squashed_sn
, corrTarget
);
402 // Squash All Branches AFTER this mispredicted branch
403 squash(squashed_sn
, tid
);
405 // If there's a squash due to a syscall, there may not be an entry
406 // corresponding to the squash. In that case, don't bother trying to
408 if (!pred_hist
.empty()) {
410 auto hist_it
= pred_hist
.begin();
411 //HistoryIt hist_it = find(pred_hist.begin(), pred_hist.end(),
414 //assert(hist_it != pred_hist.end());
415 if (pred_hist
.front().seqNum
!= squashed_sn
) {
416 DPRINTF(Branch
, "Front sn %i != Squash sn %i\n",
417 pred_hist
.front().seqNum
, squashed_sn
);
419 assert(pred_hist
.front().seqNum
== squashed_sn
);
423 if ((*hist_it
).usedRAS
) {
425 DPRINTF(Branch
, "[tid:%i]: Incorrect RAS [sn:%i]\n",
426 tid
, hist_it
->seqNum
);
429 // Get the underlying Global History Register
430 unsigned ghr
= getGHR(tid
, hist_it
->bpHistory
);
432 // There are separate functions for in-order and out-of-order
433 // branch prediction, but not for update. Therefore, this
434 // call should take into account that the mispredicted branch may
435 // be on the wrong path (i.e., OoO execution), and that the counter
436 // counter table(s) should not be updated. Thus, this call should
437 // restore the state of the underlying predictor, for instance the
438 // local/global histories. The counter tables will be updated when
439 // the branch actually commits.
441 // Remember the correct direction for the update at commit.
442 pred_hist
.front().predTaken
= actually_taken
;
444 update(tid
, (*hist_it
).pc
, actually_taken
,
445 pred_hist
.front().bpHistory
, true);
447 if (actually_taken
) {
448 if (hist_it
->wasReturn
&& !hist_it
->usedRAS
) {
449 DPRINTF(Branch
, "[tid: %i] Incorrectly predicted"
450 " return [sn:%i] PC: %s\n", tid
, hist_it
->seqNum
,
453 hist_it
->usedRAS
= true;
455 if (hist_it
->wasIndirect
) {
456 ++indirectMispredicted
;
457 iPred
.recordTarget(hist_it
->seqNum
, ghr
, corrTarget
, tid
);
459 DPRINTF(Branch
,"[tid: %i] BTB Update called for [sn:%i]"
460 " PC: %s\n", tid
,hist_it
->seqNum
, hist_it
->pc
);
462 BTB
.update((*hist_it
).pc
, corrTarget
, tid
);
466 if (hist_it
->usedRAS
) {
467 DPRINTF(Branch
,"[tid: %i] Incorrectly predicted"
468 " return [sn:%i] PC: %s Restoring RAS\n", tid
,
469 hist_it
->seqNum
, hist_it
->pc
);
470 DPRINTF(Branch
, "[tid:%i]: Restoring top of RAS"
471 " to: %i, target: %s.\n", tid
,
472 hist_it
->RASIndex
, hist_it
->RASTarget
);
473 RAS
[tid
].restore(hist_it
->RASIndex
, hist_it
->RASTarget
);
474 hist_it
->usedRAS
= false;
475 } else if (hist_it
->wasCall
&& hist_it
->pushedRAS
) {
476 //Was a Call but predicated false. Pop RAS here
477 DPRINTF(Branch
, "[tid: %i] Incorrectly predicted"
478 " Call [sn:%i] PC: %s Popping RAS\n", tid
,
479 hist_it
->seqNum
, hist_it
->pc
);
481 hist_it
->pushedRAS
= false;
485 DPRINTF(Branch
, "[tid:%i]: [sn:%i] pred_hist empty, can't "
486 "update.\n", tid
, squashed_sn
);
494 for (const auto& ph
: predHist
) {
496 auto pred_hist_it
= ph
.begin();
498 cprintf("predHist[%i].size(): %i\n", i
++, ph
.size());
500 while (pred_hist_it
!= ph
.end()) {
501 cprintf("[sn:%lli], PC:%#x, tid:%i, predTaken:%i, "
503 pred_hist_it
->seqNum
, pred_hist_it
->pc
,
504 pred_hist_it
->tid
, pred_hist_it
->predTaken
,
505 pred_hist_it
->bpHistory
);