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4 * Copyright (c) 2012 Mark D. Hill and David A. Wood
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45 #include "cpu/pred/bpred_unit.hh"
49 #include "arch/isa_traits.hh"
50 #include "arch/types.hh"
51 #include "arch/utility.hh"
52 #include "base/trace.hh"
53 #include "config/the_isa.hh"
54 #include "debug/Branch.hh"
56 BPredUnit::BPredUnit(const Params
*params
)
58 numThreads(params
->numThreads
),
60 BTB(params
->BTBEntries
,
65 useIndirect(params
->useIndirect
),
66 iPred(params
->indirectHashGHR
,
67 params
->indirectHashTargets
,
70 params
->indirectTagSize
,
71 params
->indirectPathLength
,
74 instShiftAmt(params
->instShiftAmt
)
77 r
.init(params
->RASSize
);
84 .name(name() + ".lookups")
85 .desc("Number of BP lookups")
89 .name(name() + ".condPredicted")
90 .desc("Number of conditional branches predicted")
94 .name(name() + ".condIncorrect")
95 .desc("Number of conditional branches incorrect")
99 .name(name() + ".BTBLookups")
100 .desc("Number of BTB lookups")
104 .name(name() + ".BTBHits")
105 .desc("Number of BTB hits")
109 .name(name() + ".BTBCorrect")
110 .desc("Number of correct BTB predictions (this stat may not "
115 .name(name() + ".BTBHitPct")
116 .desc("BTB Hit Percentage")
118 BTBHitPct
= (BTBHits
/ BTBLookups
) * 100;
121 .name(name() + ".usedRAS")
122 .desc("Number of times the RAS was used to get a target.")
126 .name(name() + ".RASInCorrect")
127 .desc("Number of incorrect RAS predictions.")
131 .name(name() + ".indirectLookups")
132 .desc("Number of indirect predictor lookups.")
136 .name(name() + ".indirectHits")
137 .desc("Number of indirect target hits.")
141 .name(name() + ".indirectMisses")
142 .desc("Number of indirect misses.")
146 .name(name() + "indirectMispredicted")
147 .desc("Number of mispredicted indirect branches.")
153 BPredUnit::pmuProbePoint(const char *name
)
155 ProbePoints::PMUUPtr ptr
;
156 ptr
.reset(new ProbePoints::PMU(getProbeManager(), name
));
162 BPredUnit::regProbePoints()
164 ppBranches
= pmuProbePoint("Branches");
165 ppMisses
= pmuProbePoint("Misses");
169 BPredUnit::drainSanityCheck() const
171 // We shouldn't have any outstanding requests when we resume from
173 for (const auto& ph M5_VAR_USED
: predHist
)
178 BPredUnit::predict(const StaticInstPtr
&inst
, const InstSeqNum
&seqNum
,
179 TheISA::PCState
&pc
, ThreadID tid
)
181 // See if branch predictor predicts taken.
182 // If so, get its target addr either from the BTB or the RAS.
183 // Save off record of branch stuff so the RAS can be fixed
184 // up once it's done.
186 bool pred_taken
= false;
187 TheISA::PCState target
= pc
;
190 ppBranches
->notify(1);
192 void *bp_history
= NULL
;
194 if (inst
->isUncondCtrl()) {
195 DPRINTF(Branch
, "[tid:%i]: Unconditional control.\n", tid
);
197 // Tell the BP there was an unconditional branch.
198 uncondBranch(pc
.instAddr(), bp_history
);
201 pred_taken
= lookup(pc
.instAddr(), bp_history
);
203 DPRINTF(Branch
, "[tid:%i]: [sn:%i] Branch predictor"
204 " predicted %i for PC %s\n", tid
, seqNum
, pred_taken
, pc
);
207 DPRINTF(Branch
, "[tid:%i]: [sn:%i] Creating prediction history "
208 "for PC %s\n", tid
, seqNum
, pc
);
210 PredictorHistory
predict_record(seqNum
, pc
.instAddr(),
211 pred_taken
, bp_history
, tid
);
213 // Now lookup in the BTB or RAS.
215 if (inst
->isReturn()) {
217 predict_record
.wasReturn
= true;
218 // If it's a function return call, then look up the address
220 TheISA::PCState rasTop
= RAS
[tid
].top();
221 target
= TheISA::buildRetPC(pc
, rasTop
);
223 // Record the top entry of the RAS, and its index.
224 predict_record
.usedRAS
= true;
225 predict_record
.RASIndex
= RAS
[tid
].topIdx();
226 predict_record
.RASTarget
= rasTop
;
230 DPRINTF(Branch
, "[tid:%i]: Instruction %s is a return, "
231 "RAS predicted target: %s, RAS index: %i.\n",
232 tid
, pc
, target
, predict_record
.RASIndex
);
236 if (inst
->isCall()) {
238 predict_record
.pushedRAS
= true;
240 // Record that it was a call so that the top RAS entry can
241 // be popped off if the speculation is incorrect.
242 predict_record
.wasCall
= true;
244 DPRINTF(Branch
, "[tid:%i]: Instruction %s was a "
245 "call, adding %s to the RAS index: %i.\n",
246 tid
, pc
, pc
, RAS
[tid
].topIdx());
249 if (inst
->isDirectCtrl() || !useIndirect
) {
250 // Check BTB on direct branches
251 if (BTB
.valid(pc
.instAddr(), tid
)) {
254 // If it's not a return, use the BTB to get target addr.
255 target
= BTB
.lookup(pc
.instAddr(), tid
);
257 DPRINTF(Branch
, "[tid:%i]: Instruction %s predicted"
258 " target is %s.\n", tid
, pc
, target
);
261 DPRINTF(Branch
, "[tid:%i]: BTB doesn't have a "
262 "valid entry.\n",tid
);
264 // The Direction of the branch predictor is altered
265 // because the BTB did not have an entry
266 // The predictor needs to be updated accordingly
267 if (!inst
->isCall() && !inst
->isReturn()) {
268 btbUpdate(pc
.instAddr(), bp_history
);
269 DPRINTF(Branch
, "[tid:%i]:[sn:%i] btbUpdate"
270 " called for %s\n", tid
, seqNum
, pc
);
271 } else if (inst
->isCall() && !inst
->isUncondCtrl()) {
273 predict_record
.pushedRAS
= false;
275 TheISA::advancePC(target
, inst
);
278 predict_record
.wasIndirect
= true;
280 //Consult indirect predictor on indirect control
281 if (iPred
.lookup(pc
.instAddr(), getGHR(bp_history
), target
,
283 // Indirect predictor hit
285 DPRINTF(Branch
, "[tid:%i]: Instruction %s predicted "
286 "indirect target is %s.\n", tid
, pc
, target
);
290 DPRINTF(Branch
, "[tid:%i]: Instruction %s no indirect "
291 "target.\n", tid
, pc
);
292 if (!inst
->isCall() && !inst
->isReturn()) {
294 } else if (inst
->isCall() && !inst
->isUncondCtrl()) {
296 predict_record
.pushedRAS
= false;
298 TheISA::advancePC(target
, inst
);
300 iPred
.recordIndirect(pc
.instAddr(), target
.instAddr(), seqNum
,
305 if (inst
->isReturn()) {
306 predict_record
.wasReturn
= true;
308 TheISA::advancePC(target
, inst
);
313 predHist
[tid
].push_front(predict_record
);
315 DPRINTF(Branch
, "[tid:%i]: [sn:%i]: History entry added."
316 "predHist.size(): %i\n", tid
, seqNum
, predHist
[tid
].size());
322 BPredUnit::predictInOrder(const StaticInstPtr
&inst
, const InstSeqNum
&seqNum
,
323 int asid
, TheISA::PCState
&instPC
,
324 TheISA::PCState
&predPC
, ThreadID tid
)
326 // See if branch predictor predicts taken.
327 // If so, get its target addr either from the BTB or the RAS.
328 // Save off record of branch stuff so the RAS can be fixed
329 // up once it's done.
331 using TheISA::MachInst
;
333 bool pred_taken
= false;
334 TheISA::PCState target
;
337 ppBranches
->notify(1);
339 DPRINTF(Branch
, "[tid:%i] [sn:%i] %s ... PC %s doing branch "
340 "prediction\n", tid
, seqNum
,
341 inst
->disassemble(instPC
.instAddr()), instPC
);
343 void *bp_history
= NULL
;
345 if (inst
->isUncondCtrl()) {
346 DPRINTF(Branch
, "[tid:%i] Unconditional control.\n", tid
);
348 // Tell the BP there was an unconditional branch.
349 uncondBranch(instPC
.instAddr(), bp_history
);
351 if (inst
->isReturn() && RAS
[tid
].empty()) {
352 DPRINTF(Branch
, "[tid:%i] RAS is empty, predicting "
359 pred_taken
= lookup(predPC
.instAddr(), bp_history
);
362 PredictorHistory
predict_record(seqNum
, predPC
.instAddr(), pred_taken
,
365 // Now lookup in the BTB or RAS.
367 if (inst
->isReturn()) {
370 // If it's a function return call, then look up the address
372 TheISA::PCState rasTop
= RAS
[tid
].top();
373 target
= TheISA::buildRetPC(instPC
, rasTop
);
375 // Record the top entry of the RAS, and its index.
376 predict_record
.usedRAS
= true;
377 predict_record
.RASIndex
= RAS
[tid
].topIdx();
378 predict_record
.RASTarget
= rasTop
;
380 assert(predict_record
.RASIndex
< 16);
384 DPRINTF(Branch
, "[tid:%i]: Instruction %s is a return, "
385 "RAS predicted target: %s, RAS index: %i.\n",
387 predict_record
.RASIndex
);
391 if (inst
->isCall()) {
393 RAS
[tid
].push(instPC
);
394 predict_record
.pushedRAS
= true;
396 // Record that it was a call so that the top RAS entry can
397 // be popped off if the speculation is incorrect.
398 predict_record
.wasCall
= true;
400 DPRINTF(Branch
, "[tid:%i]: Instruction %s was a call"
401 ", adding %s to the RAS index: %i.\n",
406 if (inst
->isCall() &&
407 inst
->isUncondCtrl() &&
408 inst
->isDirectCtrl()) {
409 target
= inst
->branchTarget(instPC
);
410 } else if (BTB
.valid(predPC
.instAddr(), asid
)) {
413 // If it's not a return, use the BTB to get the target addr.
414 target
= BTB
.lookup(predPC
.instAddr(), asid
);
416 DPRINTF(Branch
, "[tid:%i]: [asid:%i] Instruction %s "
417 "predicted target is %s.\n",
418 tid
, asid
, instPC
, target
);
420 DPRINTF(Branch
, "[tid:%i]: BTB doesn't have a "
421 "valid entry, predicting false.\n",tid
);
428 // Set the PC and the instruction's predicted target.
431 DPRINTF(Branch
, "[tid:%i]: [sn:%i]: Setting Predicted PC to %s.\n",
432 tid
, seqNum
, predPC
);
434 predHist
[tid
].push_front(predict_record
);
436 DPRINTF(Branch
, "[tid:%i] [sn:%i] pushed onto front of predHist "
437 "...predHist.size(): %i\n",
438 tid
, seqNum
, predHist
[tid
].size());
444 BPredUnit::update(const InstSeqNum
&done_sn
, ThreadID tid
)
446 DPRINTF(Branch
, "[tid:%i]: Committing branches until "
447 "[sn:%lli].\n", tid
, done_sn
);
449 iPred
.commit(done_sn
, tid
);
450 while (!predHist
[tid
].empty() &&
451 predHist
[tid
].back().seqNum
<= done_sn
) {
452 // Update the branch predictor with the correct results.
453 if (!predHist
[tid
].back().wasSquashed
) {
454 update(predHist
[tid
].back().pc
, predHist
[tid
].back().predTaken
,
455 predHist
[tid
].back().bpHistory
, false);
457 retireSquashed(predHist
[tid
].back().bpHistory
);
460 predHist
[tid
].pop_back();
465 BPredUnit::squash(const InstSeqNum
&squashed_sn
, ThreadID tid
)
467 History
&pred_hist
= predHist
[tid
];
469 iPred
.squash(squashed_sn
, tid
);
470 while (!pred_hist
.empty() &&
471 pred_hist
.front().seqNum
> squashed_sn
) {
472 if (pred_hist
.front().usedRAS
) {
473 DPRINTF(Branch
, "[tid:%i]: Restoring top of RAS to: %i,"
474 " target: %s.\n", tid
,
475 pred_hist
.front().RASIndex
, pred_hist
.front().RASTarget
);
477 RAS
[tid
].restore(pred_hist
.front().RASIndex
,
478 pred_hist
.front().RASTarget
);
479 } else if (pred_hist
.front().wasCall
&& pred_hist
.front().pushedRAS
) {
480 // Was a call but predicated false. Pop RAS here
481 DPRINTF(Branch
, "[tid: %i] Squashing"
482 " Call [sn:%i] PC: %s Popping RAS\n", tid
,
483 pred_hist
.front().seqNum
, pred_hist
.front().pc
);
487 // This call should delete the bpHistory.
488 squash(pred_hist
.front().bpHistory
);
490 DPRINTF(Branch
, "[tid:%i]: Removing history for [sn:%i] "
491 "PC %s.\n", tid
, pred_hist
.front().seqNum
,
492 pred_hist
.front().pc
);
494 pred_hist
.pop_front();
496 DPRINTF(Branch
, "[tid:%i]: predHist.size(): %i\n",
497 tid
, predHist
[tid
].size());
502 BPredUnit::squash(const InstSeqNum
&squashed_sn
,
503 const TheISA::PCState
&corrTarget
,
504 bool actually_taken
, ThreadID tid
)
506 // Now that we know that a branch was mispredicted, we need to undo
507 // all the branches that have been seen up until this branch and
508 // fix up everything.
509 // NOTE: This should be call conceivably in 2 scenarios:
510 // (1) After an branch is executed, it updates its status in the ROB
511 // The commit stage then checks the ROB update and sends a signal to
512 // the fetch stage to squash history after the mispredict
513 // (2) In the decode stage, you can find out early if a unconditional
514 // PC-relative, branch was predicted incorrectly. If so, a signal
515 // to the fetch stage is sent to squash history after the mispredict
517 History
&pred_hist
= predHist
[tid
];
522 DPRINTF(Branch
, "[tid:%i]: Squashing from sequence number %i, "
523 "setting target to %s.\n", tid
, squashed_sn
, corrTarget
);
525 // Squash All Branches AFTER this mispredicted branch
526 squash(squashed_sn
, tid
);
528 // If there's a squash due to a syscall, there may not be an entry
529 // corresponding to the squash. In that case, don't bother trying to
531 if (!pred_hist
.empty()) {
533 auto hist_it
= pred_hist
.begin();
534 //HistoryIt hist_it = find(pred_hist.begin(), pred_hist.end(),
537 //assert(hist_it != pred_hist.end());
538 if (pred_hist
.front().seqNum
!= squashed_sn
) {
539 DPRINTF(Branch
, "Front sn %i != Squash sn %i\n",
540 pred_hist
.front().seqNum
, squashed_sn
);
542 assert(pred_hist
.front().seqNum
== squashed_sn
);
546 if ((*hist_it
).usedRAS
) {
548 DPRINTF(Branch
, "[tid:%i]: Incorrect RAS [sn:%i]\n",
549 tid
, hist_it
->seqNum
);
552 // Have to get GHR here because the update deletes bpHistory
553 unsigned ghr
= getGHR(hist_it
->bpHistory
);
555 update((*hist_it
).pc
, actually_taken
,
556 pred_hist
.front().bpHistory
, true);
557 hist_it
->wasSquashed
= true;
559 if (actually_taken
) {
560 if (hist_it
->wasReturn
&& !hist_it
->usedRAS
) {
561 DPRINTF(Branch
, "[tid: %i] Incorrectly predicted"
562 " return [sn:%i] PC: %s\n", tid
, hist_it
->seqNum
,
565 hist_it
->usedRAS
= true;
567 if (hist_it
->wasIndirect
) {
568 ++indirectMispredicted
;
569 iPred
.recordTarget(hist_it
->seqNum
, ghr
, corrTarget
, tid
);
571 DPRINTF(Branch
,"[tid: %i] BTB Update called for [sn:%i]"
572 " PC: %s\n", tid
,hist_it
->seqNum
, hist_it
->pc
);
574 BTB
.update((*hist_it
).pc
, corrTarget
, tid
);
578 if (hist_it
->usedRAS
) {
579 DPRINTF(Branch
,"[tid: %i] Incorrectly predicted"
580 " return [sn:%i] PC: %s Restoring RAS\n", tid
,
581 hist_it
->seqNum
, hist_it
->pc
);
582 DPRINTF(Branch
, "[tid:%i]: Restoring top of RAS"
583 " to: %i, target: %s.\n", tid
,
584 hist_it
->RASIndex
, hist_it
->RASTarget
);
585 RAS
[tid
].restore(hist_it
->RASIndex
, hist_it
->RASTarget
);
586 hist_it
->usedRAS
= false;
587 } else if (hist_it
->wasCall
&& hist_it
->pushedRAS
) {
588 //Was a Call but predicated false. Pop RAS here
589 DPRINTF(Branch
, "[tid: %i] Incorrectly predicted"
590 " Call [sn:%i] PC: %s Popping RAS\n", tid
,
591 hist_it
->seqNum
, hist_it
->pc
);
593 hist_it
->pushedRAS
= false;
597 DPRINTF(Branch
, "[tid:%i]: [sn:%i] pred_hist empty, can't "
598 "update.\n", tid
, squashed_sn
);
606 for (const auto& ph
: predHist
) {
608 auto pred_hist_it
= ph
.begin();
610 cprintf("predHist[%i].size(): %i\n", i
++, ph
.size());
612 while (pred_hist_it
!= ph
.end()) {
613 cprintf("[sn:%lli], PC:%#x, tid:%i, predTaken:%i, "
615 pred_hist_it
->seqNum
, pred_hist_it
->pc
,
616 pred_hist_it
->tid
, pred_hist_it
->predTaken
,
617 pred_hist_it
->bpHistory
);