src/cpu/pred/btb.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "cpu/pred/btb.hh"
  30
  31 #include "base/intmath.hh"
  32 #include "base/trace.hh"
  33 #include "debug/Fetch.hh"
  34
  35 DefaultBTB::DefaultBTB(unsigned _numEntries,
  36                        unsigned _tagBits,
  37                        unsigned _instShiftAmt,
  38                        unsigned _num_threads)
  39     : numEntries(_numEntries),
  40       tagBits(_tagBits),
  41       instShiftAmt(_instShiftAmt),
  42       log2NumThreads(floorLog2(_num_threads))
  43 {
  44     DPRINTF(Fetch, "BTB: Creating BTB object.\n");
  45
  46     if (!isPowerOf2(numEntries)) {
  47         fatal("BTB entries is not a power of 2!");
  48     }
  49
  50     btb.resize(numEntries);
  51
  52     for (unsigned i = 0; i < numEntries; ++i) {
  53         btb[i].valid = false;
  54     }
  55
  56     idxMask = numEntries - 1;
  57
  58     tagMask = (1 << tagBits) - 1;
  59
  60     tagShiftAmt = instShiftAmt + floorLog2(numEntries);
  61 }
  62
  63 void
  64 DefaultBTB::reset()
  65 {
  66     for (unsigned i = 0; i < numEntries; ++i) {
  67         btb[i].valid = false;
  68     }
  69 }
  70
  71 inline
  72 unsigned
  73 DefaultBTB::getIndex(Addr instPC, ThreadID tid)
  74 {
  75     // Need to shift PC over by the word offset.
  76     return ((instPC >> instShiftAmt)
  77             ^ (tid << (tagShiftAmt - instShiftAmt - log2NumThreads)))
  78             & idxMask;
  79 }
  80
  81 inline
  82 Addr
  83 DefaultBTB::getTag(Addr instPC)
  84 {
  85     return (instPC >> tagShiftAmt) & tagMask;
  86 }
  87
  88 bool
  89 DefaultBTB::valid(Addr instPC, ThreadID tid)
  90 {
  91     unsigned btb_idx = getIndex(instPC, tid);
  92
  93     Addr inst_tag = getTag(instPC);
  94
  95     assert(btb_idx < numEntries);
  96
  97     if (btb[btb_idx].valid
  98         && inst_tag == btb[btb_idx].tag
  99         && btb[btb_idx].tid == tid) {
 100         return true;
 101     } else {
 102         return false;
 103     }
 104 }
 105
 106 // @todo Create some sort of return struct that has both whether or not the
 107 // address is valid, and also the address.  For now will just use addr = 0 to
 108 // represent invalid entry.
 109 TheISA::PCState
 110 DefaultBTB::lookup(Addr instPC, ThreadID tid)
 111 {
 112     unsigned btb_idx = getIndex(instPC, tid);
 113
 114     Addr inst_tag = getTag(instPC);
 115
 116     assert(btb_idx < numEntries);
 117
 118     if (btb[btb_idx].valid
 119         && inst_tag == btb[btb_idx].tag
 120         && btb[btb_idx].tid == tid) {
 121         return btb[btb_idx].target;
 122     } else {
 123         return 0;
 124     }
 125 }
 126
 127 void
 128 DefaultBTB::update(Addr instPC, const TheISA::PCState &target, ThreadID tid)
 129 {
 130     unsigned btb_idx = getIndex(instPC, tid);
 131
 132     assert(btb_idx < numEntries);
 133
 134     btb[btb_idx].tid = tid;
 135     btb[btb_idx].valid = true;
 136     btb[btb_idx].target = target;
 137     btb[btb_idx].tag = getTag(instPC);
 138 }