src/cpu/pred/btb.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "cpu/pred/btb.hh"
  32
  33 #include "base/intmath.hh"
  34 #include "base/trace.hh"
  35 #include "debug/Fetch.hh"
  36
  37 DefaultBTB::DefaultBTB(unsigned _numEntries,
  38                        unsigned _tagBits,
  39                        unsigned _instShiftAmt,
  40                        unsigned _num_threads)
  41     : numEntries(_numEntries),
  42       tagBits(_tagBits),
  43       instShiftAmt(_instShiftAmt),
  44       log2NumThreads(floorLog2(_num_threads))
  45 {
  46     DPRINTF(Fetch, "BTB: Creating BTB object.\n");
  47
  48     if (!isPowerOf2(numEntries)) {
  49         fatal("BTB entries is not a power of 2!");
  50     }
  51
  52     btb.resize(numEntries);
  53
  54     for (unsigned i = 0; i < numEntries; ++i) {
  55         btb[i].valid = false;
  56     }
  57
  58     idxMask = numEntries - 1;
  59
  60     tagMask = (1 << tagBits) - 1;
  61
  62     tagShiftAmt = instShiftAmt + floorLog2(numEntries);
  63 }
  64
  65 void
  66 DefaultBTB::reset()
  67 {
  68     for (unsigned i = 0; i < numEntries; ++i) {
  69         btb[i].valid = false;
  70     }
  71 }
  72
  73 inline
  74 unsigned
  75 DefaultBTB::getIndex(Addr instPC, ThreadID tid)
  76 {
  77     // Need to shift PC over by the word offset.
  78     return ((instPC >> instShiftAmt)
  79             ^ (tid << (tagShiftAmt - instShiftAmt - log2NumThreads)))
  80             & idxMask;
  81 }
  82
  83 inline
  84 Addr
  85 DefaultBTB::getTag(Addr instPC)
  86 {
  87     return (instPC >> tagShiftAmt) & tagMask;
  88 }
  89
  90 bool
  91 DefaultBTB::valid(Addr instPC, ThreadID tid)
  92 {
  93     unsigned btb_idx = getIndex(instPC, tid);
  94
  95     Addr inst_tag = getTag(instPC);
  96
  97     assert(btb_idx < numEntries);
  98
  99     if (btb[btb_idx].valid
 100         && inst_tag == btb[btb_idx].tag
 101         && btb[btb_idx].tid == tid) {
 102         return true;
 103     } else {
 104         return false;
 105     }
 106 }
 107
 108 // @todo Create some sort of return struct that has both whether or not the
 109 // address is valid, and also the address.  For now will just use addr = 0 to
 110 // represent invalid entry.
 111 TheISA::PCState
 112 DefaultBTB::lookup(Addr instPC, ThreadID tid)
 113 {
 114     unsigned btb_idx = getIndex(instPC, tid);
 115
 116     Addr inst_tag = getTag(instPC);
 117
 118     assert(btb_idx < numEntries);
 119
 120     if (btb[btb_idx].valid
 121         && inst_tag == btb[btb_idx].tag
 122         && btb[btb_idx].tid == tid) {
 123         return btb[btb_idx].target;
 124     } else {
 125         return 0;
 126     }
 127 }
 128
 129 void
 130 DefaultBTB::update(Addr instPC, const TheISA::PCState &target, ThreadID tid)
 131 {
 132     unsigned btb_idx = getIndex(instPC, tid);
 133
 134     assert(btb_idx < numEntries);
 135
 136     btb[btb_idx].tid = tid;
 137     btb[btb_idx].valid = true;
 138     btb[btb_idx].target = target;
 139     btb[btb_idx].tag = getTag(instPC);
 140 }