src/cpu/pred/btb.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Kevin Lim
  29  */
  30
  31 #include "base/intmath.hh"
  32 #include "base/trace.hh"
  33 #include "cpu/pred/btb.hh"
  34 #include "debug/Fetch.hh"
  35
  36 DefaultBTB::DefaultBTB(unsigned _numEntries,
  37                        unsigned _tagBits,
  38                        unsigned _instShiftAmt)
  39     : numEntries(_numEntries),
  40       tagBits(_tagBits),
  41       instShiftAmt(_instShiftAmt)
  42 {
  43     DPRINTF(Fetch, "BTB: Creating BTB object.\n");
  44
  45     if (!isPowerOf2(numEntries)) {
  46         fatal("BTB entries is not a power of 2!");
  47     }
  48
  49     btb.resize(numEntries);
  50
  51     for (unsigned i = 0; i < numEntries; ++i) {
  52         btb[i].valid = false;
  53     }
  54
  55     idxMask = numEntries - 1;
  56
  57     tagMask = (1 << tagBits) - 1;
  58
  59     tagShiftAmt = instShiftAmt + floorLog2(numEntries);
  60 }
  61
  62 void
  63 DefaultBTB::reset()
  64 {
  65     for (unsigned i = 0; i < numEntries; ++i) {
  66         btb[i].valid = false;
  67     }
  68 }
  69
  70 inline
  71 unsigned
  72 DefaultBTB::getIndex(Addr instPC)
  73 {
  74     // Need to shift PC over by the word offset.
  75     return (instPC >> instShiftAmt) & idxMask;
  76 }
  77
  78 inline
  79 Addr
  80 DefaultBTB::getTag(Addr instPC)
  81 {
  82     return (instPC >> tagShiftAmt) & tagMask;
  83 }
  84
  85 bool
  86 DefaultBTB::valid(Addr instPC, ThreadID tid)
  87 {
  88     unsigned btb_idx = getIndex(instPC);
  89
  90     Addr inst_tag = getTag(instPC);
  91
  92     assert(btb_idx < numEntries);
  93
  94     if (btb[btb_idx].valid
  95         && inst_tag == btb[btb_idx].tag
  96         && btb[btb_idx].tid == tid) {
  97         return true;
  98     } else {
  99         return false;
 100     }
 101 }
 102
 103 // @todo Create some sort of return struct that has both whether or not the
 104 // address is valid, and also the address.  For now will just use addr = 0 to
 105 // represent invalid entry.
 106 TheISA::PCState
 107 DefaultBTB::lookup(Addr instPC, ThreadID tid)
 108 {
 109     unsigned btb_idx = getIndex(instPC);
 110
 111     Addr inst_tag = getTag(instPC);
 112
 113     assert(btb_idx < numEntries);
 114
 115     if (btb[btb_idx].valid
 116         && inst_tag == btb[btb_idx].tag
 117         && btb[btb_idx].tid == tid) {
 118         return btb[btb_idx].target;
 119     } else {
 120         return 0;
 121     }
 122 }
 123
 124 void
 125 DefaultBTB::update(Addr instPC, const TheISA::PCState &target, ThreadID tid)
 126 {
 127     unsigned btb_idx = getIndex(instPC);
 128
 129     assert(btb_idx < numEntries);
 130
 131     btb[btb_idx].tid = tid;
 132     btb[btb_idx].valid = true;
 133     btb[btb_idx].target = target;
 134     btb[btb_idx].tag = getTag(instPC);
 135 }