CheckerCPU: Re-factor CheckerCPU to be compatible with current gem5
[gem5.git] / src / cpu / pred / btb.hh
1 /*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Kevin Lim
29 */
30
31 #ifndef __CPU_O3_BTB_HH__
32 #define __CPU_O3_BTB_HH__
33
34 #include "arch/types.hh"
35 #include "base/misc.hh"
36 #include "base/types.hh"
37 #include "config/the_isa.hh"
38
39 class DefaultBTB
40 {
41 private:
42 struct BTBEntry
43 {
44 BTBEntry()
45 : tag(0), target(0), valid(false)
46 {}
47
48 /** The entry's tag. */
49 Addr tag;
50
51 /** The entry's target. */
52 TheISA::PCState target;
53
54 /** The entry's thread id. */
55 ThreadID tid;
56
57 /** Whether or not the entry is valid. */
58 bool valid;
59 };
60
61 public:
62 /** Creates a BTB with the given number of entries, number of bits per
63 * tag, and instruction offset amount.
64 * @param numEntries Number of entries for the BTB.
65 * @param tagBits Number of bits for each tag in the BTB.
66 * @param instShiftAmt Offset amount for instructions to ignore alignment.
67 */
68 DefaultBTB(unsigned numEntries, unsigned tagBits,
69 unsigned instShiftAmt);
70
71 void reset();
72
73 /** Looks up an address in the BTB. Must call valid() first on the address.
74 * @param inst_PC The address of the branch to look up.
75 * @param tid The thread id.
76 * @return Returns the target of the branch.
77 */
78 TheISA::PCState lookup(Addr instPC, ThreadID tid);
79
80 /** Checks if a branch is in the BTB.
81 * @param inst_PC The address of the branch to look up.
82 * @param tid The thread id.
83 * @return Whether or not the branch exists in the BTB.
84 */
85 bool valid(Addr instPC, ThreadID tid);
86
87 /** Updates the BTB with the target of a branch.
88 * @param inst_PC The address of the branch being updated.
89 * @param target_PC The target address of the branch.
90 * @param tid The thread id.
91 */
92 void update(Addr instPC, const TheISA::PCState &targetPC,
93 ThreadID tid);
94
95 private:
96 /** Returns the index into the BTB, based on the branch's PC.
97 * @param inst_PC The branch to look up.
98 * @return Returns the index into the BTB.
99 */
100 inline unsigned getIndex(Addr instPC);
101
102 /** Returns the tag bits of a given address.
103 * @param inst_PC The branch's address.
104 * @return Returns the tag bits.
105 */
106 inline Addr getTag(Addr instPC);
107
108 /** The actual BTB. */
109 std::vector<BTBEntry> btb;
110
111 /** The number of entries in the BTB. */
112 unsigned numEntries;
113
114 /** The index mask. */
115 unsigned idxMask;
116
117 /** The number of tag bits per entry. */
118 unsigned tagBits;
119
120 /** The tag mask. */
121 unsigned tagMask;
122
123 /** Number of bits to shift PC when calculating index. */
124 unsigned instShiftAmt;
125
126 /** Number of bits to shift PC when calculating tag. */
127 unsigned tagShiftAmt;
128 };
129
130 #endif // __CPU_O3_BTB_HH__