src/cpu/pred/indirect.hh

   1 /*
   2  * Copyright (c) 2014 ARM Limited
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_PRED_INDIRECT_BASE_HH__
  30 #define __CPU_PRED_INDIRECT_BASE_HH__
  31
  32 #include "arch/types.hh"
  33 #include "config/the_isa.hh"
  34 #include "cpu/inst_seq.hh"
  35 #include "params/IndirectPredictor.hh"
  36 #include "sim/sim_object.hh"
  37
  38 class IndirectPredictor : public SimObject
  39 {
  40   public:
  41
  42     typedef IndirectPredictorParams Params;
  43
  44     IndirectPredictor(const Params *params)
  45         : SimObject(params)
  46     {
  47     }
  48
  49     virtual bool lookup(Addr br_addr, TheISA::PCState& br_target,
  50                         ThreadID tid) = 0;
  51     virtual void recordIndirect(Addr br_addr, Addr tgt_addr,
  52                                 InstSeqNum seq_num, ThreadID tid) = 0;
  53     virtual void commit(InstSeqNum seq_num, ThreadID tid,
  54                         void * indirect_history) = 0;
  55     virtual void squash(InstSeqNum seq_num, ThreadID tid) = 0;
  56     virtual void recordTarget(InstSeqNum seq_num, void * indirect_history,
  57                               const TheISA::PCState& target, ThreadID tid) = 0;
  58     virtual void genIndirectInfo(ThreadID tid, void* & indirect_history) = 0;
  59     virtual void updateDirectionInfo(ThreadID tid, bool actually_taken) = 0;
  60     virtual void deleteIndirectInfo(ThreadID tid, void * indirect_history) = 0;
  61     virtual void changeDirectionPrediction(ThreadID tid,
  62                                            void * indirect_history,
  63                                            bool actually_taken) = 0;
  64 };
  65
  66 #endif // __CPU_PRED_INDIRECT_BASE_HH__