src/cpu/reg_class.hh

   1 /*
   2  * Copyright (c) 2016-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  15  * All rights reserved
  16  *.
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Steve Reinhardt
  41  *          Nathanael Premillieu
  42  *          Rekai Gonzalez
  43  */
  44
  45 #ifndef __CPU__REG_CLASS_HH__
  46 #define __CPU__REG_CLASS_HH__
  47
  48 #include <cassert>
  49 #include <cstddef>
  50
  51 #include "arch/generic/types.hh"
  52 #include "arch/registers.hh"
  53 #include "config/the_isa.hh"
  54
  55 /** Enumerate the classes of registers. */
  56 enum RegClass {
  57     IntRegClass,        ///< Integer register
  58     FloatRegClass,      ///< Floating-point register
  59     /** Vector Register. */
  60     VecRegClass,
  61     /** Vector Register Native Elem lane. */
  62     VecElemClass,
  63     VecPredRegClass,
  64     CCRegClass,         ///< Condition-code register
  65     MiscRegClass        ///< Control (misc) register
  66 };
  67
  68 /** Number of register classes.
  69  * This value is not part of the enum, because putting it there makes the
  70  * compiler complain about unhandled cases in some switch statements.
  71  */
  72 const int NumRegClasses = MiscRegClass + 1;
  73
  74 /** Register ID: describe an architectural register with its class and index.
  75  * This structure is used instead of just the register index to disambiguate
  76  * between different classes of registers. For example, a integer register with
  77  * index 3 is represented by Regid(IntRegClass, 3).
  78  */
  79 class RegId {
  80   protected:
  81     static const char* regClassStrings[];
  82     RegClass regClass;
  83     RegIndex regIdx;
  84     ElemIndex elemIdx;
  85     static constexpr size_t Scale = TheISA::NumVecElemPerVecReg;
  86     int numPinnedWrites;
  87
  88     friend struct std::hash<RegId>;
  89
  90   public:
  91     RegId() : RegId(IntRegClass, 0) {}
  92
  93     RegId(RegClass reg_class, RegIndex reg_idx)
  94         : RegId(reg_class, reg_idx, ILLEGAL_ELEM_INDEX) {}
  95
  96     explicit RegId(RegClass reg_class, RegIndex reg_idx, ElemIndex elem_idx)
  97         : regClass(reg_class), regIdx(reg_idx), elemIdx(elem_idx),
  98           numPinnedWrites(0) {
  99         if (elemIdx == ILLEGAL_ELEM_INDEX) {
 100             panic_if(regClass == VecElemClass,
 101                     "Creating vector physical index w/o element index");
 102         } else {
 103             panic_if(regClass != VecElemClass,
 104                     "Creating non-vector physical index w/ element index");
 105         }
 106     }
 107
 108     bool operator==(const RegId& that) const {
 109         return regClass == that.classValue() && regIdx == that.index()
 110                                              && elemIdx == that.elemIndex();
 111     }
 112
 113     bool operator!=(const RegId& that) const {
 114         return !(*this==that);
 115     }
 116
 117     /** Order operator.
 118      * The order is required to implement maps with key type RegId
 119      */
 120     bool operator<(const RegId& that) const {
 121         return regClass < that.classValue() ||
 122             (regClass == that.classValue() && (
 123                    regIdx < that.index() ||
 124                    (regIdx == that.index() && elemIdx < that.elemIndex())));
 125     }
 126
 127     /**
 128      * Return true if this register can be renamed
 129      */
 130     bool isRenameable() const
 131     {
 132         return regClass != MiscRegClass;
 133     }
 134
 135     /**
 136      * Check if this is the zero register.
 137      * Returns true if this register is a zero register (needs to have a
 138      * constant zero value throughout the execution).
 139      */
 140
 141     inline bool isZeroReg() const
 142     {
 143         return regClass == IntRegClass && regIdx == TheISA::ZeroReg;
 144     }
 145
 146     /** @return true if it is an integer physical register. */
 147     bool isIntReg() const { return regClass == IntRegClass; }
 148
 149     /** @return true if it is a floating-point physical register. */
 150     bool isFloatReg() const { return regClass == FloatRegClass; }
 151
 152     /** @Return true if it is a  condition-code physical register. */
 153     bool isVecReg() const { return regClass == VecRegClass; }
 154
 155     /** @Return true if it is a  condition-code physical register. */
 156     bool isVecElem() const { return regClass == VecElemClass; }
 157
 158     /** @Return true if it is a predicate physical register. */
 159     bool isVecPredReg() const { return regClass == VecPredRegClass; }
 160
 161     /** @Return true if it is a  condition-code physical register. */
 162     bool isCCReg() const { return regClass == CCRegClass; }
 163
 164     /** @Return true if it is a  condition-code physical register. */
 165     bool isMiscReg() const { return regClass == MiscRegClass; }
 166
 167     /**
 168      * Return true if this register can be renamed
 169      */
 170     bool isRenameable()
 171     {
 172         return regClass != MiscRegClass;
 173     }
 174
 175     /** Index accessors */
 176     /** @{ */
 177     const RegIndex& index() const { return regIdx; }
 178     RegIndex& index() { return regIdx; }
 179
 180     /** Index flattening.
 181      * Required to be able to use a vector for the register mapping.
 182      */
 183     inline RegIndex flatIndex() const
 184     {
 185         switch (regClass) {
 186           case IntRegClass:
 187           case FloatRegClass:
 188           case VecRegClass:
 189           case VecPredRegClass:
 190           case CCRegClass:
 191           case MiscRegClass:
 192             return regIdx;
 193           case VecElemClass:
 194             return Scale*regIdx + elemIdx;
 195         }
 196         panic("Trying to flatten a register without class!");
 197         return -1;
 198     }
 199     /** @} */
 200
 201     /** Elem accessor */
 202     const RegIndex& elemIndex() const { return elemIdx; }
 203     /** Class accessor */
 204     const RegClass& classValue() const { return regClass; }
 205     /** Return a const char* with the register class name. */
 206     const char* className() const { return regClassStrings[regClass]; }
 207
 208     int getNumPinnedWrites() const { return numPinnedWrites; }
 209     void setNumPinnedWrites(int num_writes) { numPinnedWrites = num_writes; }
 210
 211     friend std::ostream&
 212     operator<<(std::ostream& os, const RegId& rid) {
 213         return os << rid.className() << "{" << rid.index() << "}";
 214     }
 215 };
 216
 217 /** Physical register index type.
 218  * Although the Impl might be a better for this, but there are a few classes
 219  * that need this typedef yet are not templated on the Impl.
 220  */
 221 using PhysRegIndex = short int;
 222
 223 /** Physical register ID.
 224  * Like a register ID but physical. The inheritance is private because the
 225  * only relationship between this types is functional, and it is done to
 226  * prevent code replication. */
 227 class PhysRegId : private RegId {
 228   private:
 229     PhysRegIndex flatIdx;
 230     int numPinnedWritesToComplete;
 231     bool pinned;
 232
 233   public:
 234     explicit PhysRegId() : RegId(IntRegClass, -1), flatIdx(-1),
 235                            numPinnedWritesToComplete(0)
 236     {}
 237
 238     /** Scalar PhysRegId constructor. */
 239     explicit PhysRegId(RegClass _regClass, PhysRegIndex _regIdx,
 240               PhysRegIndex _flatIdx)
 241         : RegId(_regClass, _regIdx), flatIdx(_flatIdx),
 242           numPinnedWritesToComplete(0), pinned(false)
 243     {}
 244
 245     /** Vector PhysRegId constructor (w/ elemIndex). */
 246     explicit PhysRegId(RegClass _regClass, PhysRegIndex _regIdx,
 247               ElemIndex elem_idx, PhysRegIndex flat_idx)
 248         : RegId(_regClass, _regIdx, elem_idx), flatIdx(flat_idx),
 249           numPinnedWritesToComplete(0), pinned(false)
 250     {}
 251
 252     /** Visible RegId methods */
 253     /** @{ */
 254     using RegId::index;
 255     using RegId::classValue;
 256     using RegId::isZeroReg;
 257     using RegId::className;
 258     using RegId::elemIndex;
 259      /** @} */
 260     /**
 261      * Explicit forward methods, to prevent comparisons of PhysRegId with
 262      * RegIds.
 263      */
 264     /** @{ */
 265     bool operator<(const PhysRegId& that) const {
 266         return RegId::operator<(that);
 267     }
 268
 269     bool operator==(const PhysRegId& that) const {
 270         return RegId::operator==(that);
 271     }
 272
 273     bool operator!=(const PhysRegId& that) const {
 274         return RegId::operator!=(that);
 275     }
 276     /** @} */
 277
 278     /** @return true if it is an integer physical register. */
 279     bool isIntPhysReg() const { return isIntReg(); }
 280
 281     /** @return true if it is a floating-point physical register. */
 282     bool isFloatPhysReg() const { return isFloatReg(); }
 283
 284     /** @Return true if it is a  condition-code physical register. */
 285     bool isCCPhysReg() const { return isCCReg(); }
 286
 287     /** @Return true if it is a vector physical register. */
 288     bool isVectorPhysReg() const { return isVecReg(); }
 289
 290     /** @Return true if it is a vector element physical register. */
 291     bool isVectorPhysElem() const { return isVecElem(); }
 292
 293     /** @return true if it is a vector predicate physical register. */
 294     bool isVecPredPhysReg() const { return isVecPredReg(); }
 295
 296     /** @Return true if it is a  condition-code physical register. */
 297     bool isMiscPhysReg() const { return isMiscReg(); }
 298
 299     /**
 300      * Returns true if this register is always associated to the same
 301      * architectural register.
 302      */
 303     bool isFixedMapping() const
 304     {
 305         return !isRenameable();
 306     }
 307
 308     /** Flat index accessor */
 309     const PhysRegIndex& flatIndex() const { return flatIdx; }
 310
 311     static PhysRegId elemId(PhysRegId* vid, ElemIndex elem)
 312     {
 313         assert(vid->isVectorPhysReg());
 314         return PhysRegId(VecElemClass, vid->index(), elem);
 315     }
 316
 317     int getNumPinnedWrites() const { return numPinnedWrites; }
 318
 319     void setNumPinnedWrites(int numWrites)
 320     {
 321         // An instruction with a pinned destination reg can get
 322         // squashed. The numPinnedWrites counter may be zero when
 323         // the squash happens but we need to know if the dest reg
 324         // was pinned originally in order to reset counters properly
 325         // for a possible re-rename using the same physical reg (which
 326         // may be required in case of a mem access order violation).
 327         pinned = (numWrites != 0);
 328         numPinnedWrites = numWrites;
 329     }
 330
 331     void decrNumPinnedWrites() { --numPinnedWrites; }
 332     void incrNumPinnedWrites() { ++numPinnedWrites; }
 333
 334     bool isPinned() const { return pinned; }
 335
 336     int getNumPinnedWritesToComplete() const
 337     {
 338         return numPinnedWritesToComplete;
 339     }
 340
 341     void setNumPinnedWritesToComplete(int numWrites)
 342     {
 343         numPinnedWritesToComplete = numWrites;
 344     }
 345
 346     void decrNumPinnedWritesToComplete() { --numPinnedWritesToComplete; }
 347     void incrNumPinnedWritesToComplete() { ++numPinnedWritesToComplete; }
 348 };
 349
 350 using PhysRegIdPtr = PhysRegId*;
 351
 352 namespace std
 353 {
 354 template<>
 355 struct hash<RegId>
 356 {
 357     size_t operator()(const RegId& reg_id) const
 358     {
 359         // Extract unique integral values for the effective fields of a RegId.
 360         const size_t flat_index = static_cast<size_t>(reg_id.flatIndex());
 361         const size_t class_num = static_cast<size_t>(reg_id.regClass);
 362
 363         const size_t shifted_class_num = class_num << (sizeof(RegIndex) << 3);
 364
 365         // Concatenate the class_num to the end of the flat_index, in order to
 366         // maximize information retained.
 367         const size_t concatenated_hash = flat_index | shifted_class_num;
 368
 369         // If RegIndex is larger than size_t, then class_num will not be
 370         // considered by this hash function, so we may wish to perform a
 371         // different operation to include that information in the hash.
 372         static_assert(sizeof(RegIndex) < sizeof(size_t),
 373             "sizeof(RegIndex) should be less than sizeof(size_t)");
 374
 375         return concatenated_hash;
 376     }
 377 };
 378 }
 379
 380 #endif // __CPU__REG_CLASS_HH__