src/cpu/reg_class_impl.hh

   1 /*
   2  * Copyright (c) 2016 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Rekai Gonzalez
  38  */
  39
  40 #ifndef __CPU__REG_CLASS_IMPL_HH__
  41 #define __CPU__REG_CLASS_IMPL_HH__
  42
  43 #include <cassert>
  44 #include <cstddef>
  45 #include <iostream>
  46
  47 #include "arch/registers.hh"
  48 #include "config/the_isa.hh"
  49 #include "cpu/reg_class.hh"
  50
  51 bool RegId::isZeroReg() const
  52 {
  53     return ((regClass == IntRegClass && regIdx == TheISA::ZeroReg) ||
  54             (THE_ISA == ALPHA_ISA && regClass == FloatRegClass &&
  55              regIdx == TheISA::ZeroReg));
  56 }
  57
  58 static constexpr size_t Scale = TheISA::NumVecElemPerVecReg;
  59
  60 RegIndex RegId::flatIndex() const {
  61     switch (regClass) {
  62     case IntRegClass:
  63     case FloatRegClass:
  64     case VecRegClass:
  65     case CCRegClass:
  66     case MiscRegClass:
  67         return regIdx;
  68     case VecElemClass:
  69         return Scale*regIdx + elemIdx;
  70     }
  71     panic("Trying to flatten a register without class!");
  72     return -1;
  73 }
  74
  75 #endif // __CPU__REG_CLASS_IMPL_HH__