src/cpu/simple/AtomicSimpleCPU.py

   1 # Copyright (c) 2007 The Regents of The University of Michigan
   2 # All rights reserved.
   3 #
   4 # Redistribution and use in source and binary forms, with or without
   5 # modification, are permitted provided that the following conditions are
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   7 # notice, this list of conditions and the following disclaimer;
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   9 # notice, this list of conditions and the following disclaimer in the
  10 # documentation and/or other materials provided with the distribution;
  11 # neither the name of the copyright holders nor the names of its
  12 # contributors may be used to endorse or promote products derived from
  13 # this software without specific prior written permission.
  14 #
  15 # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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  19 # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  25 # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 #
  27 # Authors: Nathan Binkert
  28
  29 from m5.params import *
  30 from m5 import build_env
  31 from BaseCPU import BaseCPU
  32
  33 class AtomicSimpleCPU(BaseCPU):
  34     type = 'AtomicSimpleCPU'
  35     width = Param.Int(1, "CPU width")
  36     simulate_stalls = Param.Bool(False, "Simulate cache stall cycles")
  37     function_trace = Param.Bool(False, "Enable function trace")
  38     function_trace_start = Param.Tick(0, "Cycle to start function trace")
  39     if build_env['FULL_SYSTEM']:
  40         profile = Param.Latency('0ns', "trace the kernel stack")
  41     icache_port = Port("Instruction Port")
  42     dcache_port = Port("Data Port")
  43     _mem_ports = ['icache_port', 'dcache_port']