src/cpu/simple/atomic.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #include "arch/utility.hh"
  32 #include "cpu/exetrace.hh"
  33 #include "cpu/simple/atomic.hh"
  34 #include "mem/packet_impl.hh"
  35 #include "sim/builder.hh"
  36 #include "sim/system.hh"
  37
  38 using namespace std;
  39 using namespace TheISA;
  40
  41 AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
  42     : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
  43 {
  44 }
  45
  46
  47 void
  48 AtomicSimpleCPU::TickEvent::process()
  49 {
  50     cpu->tick();
  51 }
  52
  53 const char *
  54 AtomicSimpleCPU::TickEvent::description()
  55 {
  56     return "AtomicSimpleCPU tick event";
  57 }
  58
  59 Port *
  60 AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
  61 {
  62     if (if_name == "dcache_port")
  63         return &dcachePort;
  64     else if (if_name == "icache_port")
  65         return &icachePort;
  66     else
  67         panic("No Such Port\n");
  68 }
  69
  70 void
  71 AtomicSimpleCPU::init()
  72 {
  73     //Create Memory Ports (conect them up)
  74 //    Port *mem_dport = mem->getPort("");
  75 //    dcachePort.setPeer(mem_dport);
  76 //    mem_dport->setPeer(&dcachePort);
  77
  78 //    Port *mem_iport = mem->getPort("");
  79 //    icachePort.setPeer(mem_iport);
  80 //    mem_iport->setPeer(&icachePort);
  81
  82     BaseCPU::init();
  83 #if FULL_SYSTEM
  84     for (int i = 0; i < threadContexts.size(); ++i) {
  85         ThreadContext *tc = threadContexts[i];
  86
  87         // initialize CPU, including PC
  88         TheISA::initCPU(tc, tc->readCpuId());
  89     }
  90 #endif
  91 }
  92
  93 bool
  94 AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
  95 {
  96     panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
  97     return true;
  98 }
  99
 100 Tick
 101 AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
 102 {
 103     panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
 104     return curTick;
 105 }
 106
 107 void
 108 AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
 109 {
 110     panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
 111 }
 112
 113 void
 114 AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
 115 {
 116     if (status == RangeChange)
 117         return;
 118
 119     panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
 120 }
 121
 122 void
 123 AtomicSimpleCPU::CpuPort::recvRetry()
 124 {
 125     panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
 126 }
 127
 128
 129 AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
 130     : BaseSimpleCPU(p), tickEvent(this),
 131       width(p->width), simulate_stalls(p->simulate_stalls),
 132       icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
 133 {
 134     _status = Idle;
 135
 136     // @todo fix me and get the real cpu id & thread number!!!
 137     ifetch_req = new Request();
 138     ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
 139     ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
 140     ifetch_pkt->dataStatic(&inst);
 141
 142     data_read_req = new Request();
 143     data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
 144     data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
 145                                Packet::Broadcast);
 146     data_read_pkt->dataStatic(&dataReg);
 147
 148     data_write_req = new Request();
 149     data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
 150     data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
 151                                 Packet::Broadcast);
 152 }
 153
 154
 155 AtomicSimpleCPU::~AtomicSimpleCPU()
 156 {
 157 }
 158
 159 void
 160 AtomicSimpleCPU::serialize(ostream &os)
 161 {
 162     SimObject::State so_state = SimObject::getState();
 163     SERIALIZE_ENUM(so_state);
 164     nameOut(os, csprintf("%s.tickEvent", name()));
 165     tickEvent.serialize(os);
 166     BaseSimpleCPU::serialize(os);
 167 }
 168
 169 void
 170 AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 171 {
 172     SimObject::State so_state;
 173     UNSERIALIZE_ENUM(so_state);
 174     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
 175     BaseSimpleCPU::unserialize(cp, section);
 176 }
 177
 178 void
 179 AtomicSimpleCPU::resume()
 180 {
 181     assert(system->getMemoryMode() == System::Atomic);
 182     changeState(SimObject::Running);
 183     if (thread->status() == ThreadContext::Active) {
 184         if (!tickEvent.scheduled())
 185             tickEvent.schedule(curTick);
 186     }
 187 }
 188
 189 void
 190 AtomicSimpleCPU::switchOut()
 191 {
 192     assert(status() == Running || status() == Idle);
 193     _status = SwitchedOut;
 194
 195     tickEvent.squash();
 196 }
 197
 198
 199 void
 200 AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 201 {
 202     BaseCPU::takeOverFrom(oldCPU);
 203
 204     assert(!tickEvent.scheduled());
 205
 206     // if any of this CPU's ThreadContexts are active, mark the CPU as
 207     // running and schedule its tick event.
 208     for (int i = 0; i < threadContexts.size(); ++i) {
 209         ThreadContext *tc = threadContexts[i];
 210         if (tc->status() == ThreadContext::Active && _status != Running) {
 211             _status = Running;
 212             tickEvent.schedule(curTick);
 213             break;
 214         }
 215     }
 216 }
 217
 218
 219 void
 220 AtomicSimpleCPU::activateContext(int thread_num, int delay)
 221 {
 222     assert(thread_num == 0);
 223     assert(thread);
 224
 225     assert(_status == Idle);
 226     assert(!tickEvent.scheduled());
 227
 228     notIdleFraction++;
 229     tickEvent.schedule(curTick + cycles(delay));
 230     _status = Running;
 231 }
 232
 233
 234 void
 235 AtomicSimpleCPU::suspendContext(int thread_num)
 236 {
 237     assert(thread_num == 0);
 238     assert(thread);
 239
 240     assert(_status == Running);
 241
 242     // tick event may not be scheduled if this gets called from inside
 243     // an instruction's execution, e.g. "quiesce"
 244     if (tickEvent.scheduled())
 245         tickEvent.deschedule();
 246
 247     notIdleFraction--;
 248     _status = Idle;
 249 }
 250
 251
 252 template <class T>
 253 Fault
 254 AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
 255 {
 256     data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 257
 258     if (traceData) {
 259         traceData->setAddr(addr);
 260     }
 261
 262     // translate to physical address
 263     Fault fault = thread->translateDataReadReq(data_read_req);
 264
 265     // Now do the access.
 266     if (fault == NoFault) {
 267         data_read_pkt->reinitFromRequest();
 268
 269         dcache_latency = dcachePort.sendAtomic(data_read_pkt);
 270         dcache_access = true;
 271
 272         assert(data_read_pkt->result == Packet::Success);
 273         data = data_read_pkt->get<T>();
 274
 275     }
 276
 277     // This will need a new way to tell if it has a dcache attached.
 278     if (data_read_req->getFlags() & UNCACHEABLE)
 279         recordEvent("Uncached Read");
 280
 281     return fault;
 282 }
 283
 284 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 285
 286 template
 287 Fault
 288 AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
 289
 290 template
 291 Fault
 292 AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
 293
 294 template
 295 Fault
 296 AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
 297
 298 template
 299 Fault
 300 AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
 301
 302 #endif //DOXYGEN_SHOULD_SKIP_THIS
 303
 304 template<>
 305 Fault
 306 AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
 307 {
 308     return read(addr, *(uint64_t*)&data, flags);
 309 }
 310
 311 template<>
 312 Fault
 313 AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
 314 {
 315     return read(addr, *(uint32_t*)&data, flags);
 316 }
 317
 318
 319 template<>
 320 Fault
 321 AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
 322 {
 323     return read(addr, (uint32_t&)data, flags);
 324 }
 325
 326
 327 template <class T>
 328 Fault
 329 AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 330 {
 331     data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 332
 333     if (traceData) {
 334         traceData->setAddr(addr);
 335     }
 336
 337     // translate to physical address
 338     Fault fault = thread->translateDataWriteReq(data_write_req);
 339
 340     // Now do the access.
 341     if (fault == NoFault) {
 342         data = htog(data);
 343         data_write_pkt->reinitFromRequest();
 344         data_write_pkt->dataStatic(&data);
 345
 346         dcache_latency = dcachePort.sendAtomic(data_write_pkt);
 347         dcache_access = true;
 348
 349         assert(data_write_pkt->result == Packet::Success);
 350
 351         if (res && data_write_req->getFlags() & LOCKED) {
 352             *res = data_write_req->getScResult();
 353         }
 354     }
 355
 356     // This will need a new way to tell if it's hooked up to a cache or not.
 357     if (data_write_req->getFlags() & UNCACHEABLE)
 358         recordEvent("Uncached Write");
 359
 360     // If the write needs to have a fault on the access, consider calling
 361     // changeStatus() and changing it to "bad addr write" or something.
 362     return fault;
 363 }
 364
 365
 366 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 367 template
 368 Fault
 369 AtomicSimpleCPU::write(uint64_t data, Addr addr,
 370                        unsigned flags, uint64_t *res);
 371
 372 template
 373 Fault
 374 AtomicSimpleCPU::write(uint32_t data, Addr addr,
 375                        unsigned flags, uint64_t *res);
 376
 377 template
 378 Fault
 379 AtomicSimpleCPU::write(uint16_t data, Addr addr,
 380                        unsigned flags, uint64_t *res);
 381
 382 template
 383 Fault
 384 AtomicSimpleCPU::write(uint8_t data, Addr addr,
 385                        unsigned flags, uint64_t *res);
 386
 387 #endif //DOXYGEN_SHOULD_SKIP_THIS
 388
 389 template<>
 390 Fault
 391 AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
 392 {
 393     return write(*(uint64_t*)&data, addr, flags, res);
 394 }
 395
 396 template<>
 397 Fault
 398 AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
 399 {
 400     return write(*(uint32_t*)&data, addr, flags, res);
 401 }
 402
 403
 404 template<>
 405 Fault
 406 AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 407 {
 408     return write((uint32_t)data, addr, flags, res);
 409 }
 410
 411
 412 void
 413 AtomicSimpleCPU::tick()
 414 {
 415     Tick latency = cycles(1); // instruction takes one cycle by default
 416
 417     for (int i = 0; i < width; ++i) {
 418         numCycles++;
 419
 420         checkForInterrupts();
 421
 422         Fault fault = setupFetchRequest(ifetch_req);
 423
 424         if (fault == NoFault) {
 425             ifetch_pkt->reinitFromRequest();
 426
 427             Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
 428             // ifetch_req is initialized to read the instruction directly
 429             // into the CPU object's inst field.
 430
 431             dcache_access = false; // assume no dcache access
 432             preExecute();
 433             fault = curStaticInst->execute(this, traceData);
 434             postExecute();
 435
 436             if (simulate_stalls) {
 437                 Tick icache_stall = icache_latency - cycles(1);
 438                 Tick dcache_stall =
 439                     dcache_access ? dcache_latency - cycles(1) : 0;
 440                 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
 441                 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
 442                     latency += cycles(stall_cycles+1);
 443                 else
 444                     latency += cycles(stall_cycles);
 445             }
 446
 447         }
 448
 449         advancePC(fault);
 450     }
 451
 452     if (_status != Idle)
 453         tickEvent.schedule(curTick + latency);
 454 }
 455
 456
 457 ////////////////////////////////////////////////////////////////////////
 458 //
 459 //  AtomicSimpleCPU Simulation Object
 460 //
 461 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
 462
 463     Param<Counter> max_insts_any_thread;
 464     Param<Counter> max_insts_all_threads;
 465     Param<Counter> max_loads_any_thread;
 466     Param<Counter> max_loads_all_threads;
 467     SimObjectParam<MemObject *> mem;
 468     SimObjectParam<System *> system;
 469
 470 #if FULL_SYSTEM
 471     SimObjectParam<AlphaITB *> itb;
 472     SimObjectParam<AlphaDTB *> dtb;
 473     Param<int> cpu_id;
 474     Param<Tick> profile;
 475 #else
 476     SimObjectParam<Process *> workload;
 477 #endif // FULL_SYSTEM
 478
 479     Param<int> clock;
 480
 481     Param<bool> defer_registration;
 482     Param<int> width;
 483     Param<bool> function_trace;
 484     Param<Tick> function_trace_start;
 485     Param<bool> simulate_stalls;
 486
 487 END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
 488
 489 BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
 490
 491     INIT_PARAM(max_insts_any_thread,
 492                "terminate when any thread reaches this inst count"),
 493     INIT_PARAM(max_insts_all_threads,
 494                "terminate when all threads have reached this inst count"),
 495     INIT_PARAM(max_loads_any_thread,
 496                "terminate when any thread reaches this load count"),
 497     INIT_PARAM(max_loads_all_threads,
 498                "terminate when all threads have reached this load count"),
 499     INIT_PARAM(mem, "memory"),
 500     INIT_PARAM(system, "system object"),
 501
 502 #if FULL_SYSTEM
 503     INIT_PARAM(itb, "Instruction TLB"),
 504     INIT_PARAM(dtb, "Data TLB"),
 505     INIT_PARAM(cpu_id, "processor ID"),
 506     INIT_PARAM(profile, ""),
 507 #else
 508     INIT_PARAM(workload, "processes to run"),
 509 #endif // FULL_SYSTEM
 510
 511     INIT_PARAM(clock, "clock speed"),
 512     INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
 513     INIT_PARAM(width, "cpu width"),
 514     INIT_PARAM(function_trace, "Enable function trace"),
 515     INIT_PARAM(function_trace_start, "Cycle to start function trace"),
 516     INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
 517
 518 END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
 519
 520
 521 CREATE_SIM_OBJECT(AtomicSimpleCPU)
 522 {
 523     AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
 524     params->name = getInstanceName();
 525     params->numberOfThreads = 1;
 526     params->max_insts_any_thread = max_insts_any_thread;
 527     params->max_insts_all_threads = max_insts_all_threads;
 528     params->max_loads_any_thread = max_loads_any_thread;
 529     params->max_loads_all_threads = max_loads_all_threads;
 530     params->deferRegistration = defer_registration;
 531     params->clock = clock;
 532     params->functionTrace = function_trace;
 533     params->functionTraceStart = function_trace_start;
 534     params->width = width;
 535     params->simulate_stalls = simulate_stalls;
 536     params->mem = mem;
 537     params->system = system;
 538
 539 #if FULL_SYSTEM
 540     params->itb = itb;
 541     params->dtb = dtb;
 542     params->cpu_id = cpu_id;
 543     params->profile = profile;
 544 #else
 545     params->process = workload;
 546 #endif
 547
 548     AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
 549     return cpu;
 550 }
 551
 552 REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
 553