f3596b6a5fd6ea8170a87ca4f9ea4aaa3edec32f
2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2012-2013,2015,2017 ARM Limited
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
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15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
44 #include "cpu/simple/atomic.hh"
46 #include "arch/locked_mem.hh"
47 #include "arch/mmapped_ipr.hh"
48 #include "arch/utility.hh"
49 #include "base/bigint.hh"
50 #include "base/output.hh"
51 #include "config/the_isa.hh"
52 #include "cpu/exetrace.hh"
53 #include "debug/Drain.hh"
54 #include "debug/ExecFaulting.hh"
55 #include "debug/SimpleCPU.hh"
56 #include "mem/packet.hh"
57 #include "mem/packet_access.hh"
58 #include "mem/physical.hh"
59 #include "params/AtomicSimpleCPU.hh"
60 #include "sim/faults.hh"
61 #include "sim/full_system.hh"
62 #include "sim/system.hh"
65 using namespace TheISA
;
68 AtomicSimpleCPU::init()
70 BaseSimpleCPU::init();
72 int cid
= threadContexts
[0]->contextId();
73 ifetch_req
.setContext(cid
);
74 data_read_req
.setContext(cid
);
75 data_write_req
.setContext(cid
);
78 AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams
*p
)
80 tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick",
81 false, Event::CPU_Tick_Pri
),
82 width(p
->width
), locked(false),
83 simulate_data_stalls(p
->simulate_data_stalls
),
84 simulate_inst_stalls(p
->simulate_inst_stalls
),
85 icachePort(name() + ".icache_port", this),
86 dcachePort(name() + ".dcache_port", this),
87 fastmem(p
->fastmem
), dcache_access(false), dcache_latency(0),
94 AtomicSimpleCPU::~AtomicSimpleCPU()
96 if (tickEvent
.scheduled()) {
97 deschedule(tickEvent
);
102 AtomicSimpleCPU::drain()
104 // Deschedule any power gating event (if any)
105 deschedulePowerGatingEvent();
108 return DrainState::Drained
;
111 DPRINTF(Drain
, "Requesting drain.\n");
112 return DrainState::Draining
;
114 if (tickEvent
.scheduled())
115 deschedule(tickEvent
);
117 activeThreads
.clear();
118 DPRINTF(Drain
, "Not executing microcode, no need to drain.\n");
119 return DrainState::Drained
;
124 AtomicSimpleCPU::threadSnoop(PacketPtr pkt
, ThreadID sender
)
126 DPRINTF(SimpleCPU
, "received snoop pkt for addr:%#x %s\n", pkt
->getAddr(),
129 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
131 if (getCpuAddrMonitor(tid
)->doMonitor(pkt
)) {
135 TheISA::handleLockedSnoop(threadInfo
[tid
]->thread
,
136 pkt
, dcachePort
.cacheBlockMask
);
142 AtomicSimpleCPU::drainResume()
144 assert(!tickEvent
.scheduled());
148 DPRINTF(SimpleCPU
, "Resume\n");
151 assert(!threadContexts
.empty());
153 _status
= BaseSimpleCPU::Idle
;
155 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
156 if (threadInfo
[tid
]->thread
->status() == ThreadContext::Active
) {
157 threadInfo
[tid
]->notIdleFraction
= 1;
158 activeThreads
.push_back(tid
);
159 _status
= BaseSimpleCPU::Running
;
161 // Tick if any threads active
162 if (!tickEvent
.scheduled()) {
163 schedule(tickEvent
, nextCycle());
166 threadInfo
[tid
]->notIdleFraction
= 0;
170 // Reschedule any power gating event (if any)
171 schedulePowerGatingEvent();
175 AtomicSimpleCPU::tryCompleteDrain()
177 if (drainState() != DrainState::Draining
)
180 DPRINTF(Drain
, "tryCompleteDrain.\n");
184 DPRINTF(Drain
, "CPU done draining, processing drain event\n");
192 AtomicSimpleCPU::switchOut()
194 BaseSimpleCPU::switchOut();
196 assert(!tickEvent
.scheduled());
197 assert(_status
== BaseSimpleCPU::Running
|| _status
== Idle
);
203 AtomicSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
205 BaseSimpleCPU::takeOverFrom(oldCPU
);
207 // The tick event should have been descheduled by drain()
208 assert(!tickEvent
.scheduled());
212 AtomicSimpleCPU::verifyMemoryMode() const
214 if (!system
->isAtomicMode()) {
215 fatal("The atomic CPU requires the memory system to be in "
221 AtomicSimpleCPU::activateContext(ThreadID thread_num
)
223 DPRINTF(SimpleCPU
, "ActivateContext %d\n", thread_num
);
225 assert(thread_num
< numThreads
);
227 threadInfo
[thread_num
]->notIdleFraction
= 1;
228 Cycles delta
= ticksToCycles(threadInfo
[thread_num
]->thread
->lastActivate
-
229 threadInfo
[thread_num
]->thread
->lastSuspend
);
232 if (!tickEvent
.scheduled()) {
233 //Make sure ticks are still on multiples of cycles
234 schedule(tickEvent
, clockEdge(Cycles(0)));
236 _status
= BaseSimpleCPU::Running
;
237 if (std::find(activeThreads
.begin(), activeThreads
.end(), thread_num
)
238 == activeThreads
.end()) {
239 activeThreads
.push_back(thread_num
);
242 BaseCPU::activateContext(thread_num
);
247 AtomicSimpleCPU::suspendContext(ThreadID thread_num
)
249 DPRINTF(SimpleCPU
, "SuspendContext %d\n", thread_num
);
251 assert(thread_num
< numThreads
);
252 activeThreads
.remove(thread_num
);
257 assert(_status
== BaseSimpleCPU::Running
);
259 threadInfo
[thread_num
]->notIdleFraction
= 0;
261 if (activeThreads
.empty()) {
264 if (tickEvent
.scheduled()) {
265 deschedule(tickEvent
);
269 BaseCPU::suspendContext(thread_num
);
274 AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt
)
276 DPRINTF(SimpleCPU
, "received snoop pkt for addr:%#x %s\n", pkt
->getAddr(),
279 // X86 ISA: Snooping an invalidation for monitor/mwait
280 AtomicSimpleCPU
*cpu
= (AtomicSimpleCPU
*)(&owner
);
282 for (ThreadID tid
= 0; tid
< cpu
->numThreads
; tid
++) {
283 if (cpu
->getCpuAddrMonitor(tid
)->doMonitor(pkt
)) {
288 // if snoop invalidates, release any associated locks
289 // When run without caches, Invalidation packets will not be received
290 // hence we must check if the incoming packets are writes and wakeup
291 // the processor accordingly
292 if (pkt
->isInvalidate() || pkt
->isWrite()) {
293 DPRINTF(SimpleCPU
, "received invalidation for addr:%#x\n",
295 for (auto &t_info
: cpu
->threadInfo
) {
296 TheISA::handleLockedSnoop(t_info
->thread
, pkt
, cacheBlockMask
);
304 AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt
)
306 DPRINTF(SimpleCPU
, "received snoop pkt for addr:%#x %s\n", pkt
->getAddr(),
309 // X86 ISA: Snooping an invalidation for monitor/mwait
310 AtomicSimpleCPU
*cpu
= (AtomicSimpleCPU
*)(&owner
);
311 for (ThreadID tid
= 0; tid
< cpu
->numThreads
; tid
++) {
312 if (cpu
->getCpuAddrMonitor(tid
)->doMonitor(pkt
)) {
317 // if snoop invalidates, release any associated locks
318 if (pkt
->isInvalidate()) {
319 DPRINTF(SimpleCPU
, "received invalidation for addr:%#x\n",
321 for (auto &t_info
: cpu
->threadInfo
) {
322 TheISA::handleLockedSnoop(t_info
->thread
, pkt
, cacheBlockMask
);
328 AtomicSimpleCPU::readMem(Addr addr
, uint8_t * data
, unsigned size
,
329 Request::Flags flags
)
331 SimpleExecContext
& t_info
= *threadInfo
[curThread
];
332 SimpleThread
* thread
= t_info
.thread
;
334 // use the CPU's statically allocated read request and packet objects
335 Request
*req
= &data_read_req
;
338 traceData
->setMem(addr
, size
, flags
);
340 //The size of the data we're trying to read.
343 //The address of the second part of this access if it needs to be split
344 //across a cache line boundary.
345 Addr secondAddr
= roundDown(addr
+ size
- 1, cacheLineSize());
347 if (secondAddr
> addr
)
348 size
= secondAddr
- addr
;
352 req
->taskId(taskId());
354 req
->setVirt(0, addr
, size
, flags
, dataMasterId(), thread
->pcState().instAddr());
356 // translate to physical address
357 Fault fault
= thread
->dtb
->translateAtomic(req
, thread
->getTC(),
360 // Now do the access.
361 if (fault
== NoFault
&& !req
->getFlags().isSet(Request::NO_ACCESS
)) {
362 Packet
pkt(req
, Packet::makeReadCmd(req
));
363 pkt
.dataStatic(data
);
365 if (req
->isMmappedIpr())
366 dcache_latency
+= TheISA::handleIprRead(thread
->getTC(), &pkt
);
368 if (fastmem
&& system
->isMemAddr(pkt
.getAddr()))
369 system
->getPhysMem().access(&pkt
);
371 dcache_latency
+= dcachePort
.sendAtomic(&pkt
);
373 dcache_access
= true;
375 assert(!pkt
.isError());
378 TheISA::handleLockedRead(thread
, req
);
382 //If there's a fault, return it
383 if (fault
!= NoFault
) {
384 if (req
->isPrefetch()) {
391 //If we don't need to access a second cache line, stop now.
392 if (secondAddr
<= addr
)
394 if (req
->isLockedRMW() && fault
== NoFault
) {
403 * Set up for accessing the second cache line.
406 //Move the pointer we're reading into to the correct location.
408 //Adjust the size to get the remaining bytes.
409 size
= addr
+ fullSize
- secondAddr
;
410 //And access the right address.
416 AtomicSimpleCPU::initiateMemRead(Addr addr
, unsigned size
,
417 Request::Flags flags
)
419 panic("initiateMemRead() is for timing accesses, and should "
420 "never be called on AtomicSimpleCPU.\n");
424 AtomicSimpleCPU::writeMem(uint8_t *data
, unsigned size
, Addr addr
,
425 Request::Flags flags
, uint64_t *res
)
427 SimpleExecContext
& t_info
= *threadInfo
[curThread
];
428 SimpleThread
* thread
= t_info
.thread
;
429 static uint8_t zero_array
[64] = {};
433 assert(flags
& Request::STORE_NO_DATA
);
434 // This must be a cache block cleaning request
438 // use the CPU's statically allocated write request and packet objects
439 Request
*req
= &data_write_req
;
442 traceData
->setMem(addr
, size
, flags
);
444 //The size of the data we're trying to read.
447 //The address of the second part of this access if it needs to be split
448 //across a cache line boundary.
449 Addr secondAddr
= roundDown(addr
+ size
- 1, cacheLineSize());
451 if (secondAddr
> addr
)
452 size
= secondAddr
- addr
;
456 req
->taskId(taskId());
458 req
->setVirt(0, addr
, size
, flags
, dataMasterId(), thread
->pcState().instAddr());
460 // translate to physical address
461 Fault fault
= thread
->dtb
->translateAtomic(req
, thread
->getTC(), BaseTLB::Write
);
463 // Now do the access.
464 if (fault
== NoFault
) {
465 bool do_access
= true; // flag to suppress cache access
468 do_access
= TheISA::handleLockedWrite(thread
, req
, dcachePort
.cacheBlockMask
);
469 } else if (req
->isSwap()) {
470 if (req
->isCondSwap()) {
472 req
->setExtraData(*res
);
476 if (do_access
&& !req
->getFlags().isSet(Request::NO_ACCESS
)) {
477 Packet
pkt(req
, Packet::makeWriteCmd(req
));
478 pkt
.dataStatic(data
);
480 if (req
->isMmappedIpr()) {
482 TheISA::handleIprWrite(thread
->getTC(), &pkt
);
484 if (fastmem
&& system
->isMemAddr(pkt
.getAddr()))
485 system
->getPhysMem().access(&pkt
);
487 dcache_latency
+= dcachePort
.sendAtomic(&pkt
);
489 // Notify other threads on this CPU of write
490 threadSnoop(&pkt
, curThread
);
492 dcache_access
= true;
493 assert(!pkt
.isError());
497 memcpy(res
, pkt
.getConstPtr
<uint8_t>(), fullSize
);
501 if (res
&& !req
->isSwap()) {
502 *res
= req
->getExtraData();
506 //If there's a fault or we don't need to access a second cache line,
508 if (fault
!= NoFault
|| secondAddr
<= addr
)
510 if (req
->isLockedRMW() && fault
== NoFault
) {
516 if (fault
!= NoFault
&& req
->isPrefetch()) {
524 * Set up for accessing the second cache line.
527 //Move the pointer we're reading into to the correct location.
529 //Adjust the size to get the remaining bytes.
530 size
= addr
+ fullSize
- secondAddr
;
531 //And access the right address.
538 AtomicSimpleCPU::tick()
540 DPRINTF(SimpleCPU
, "Tick\n");
542 // Change thread if multi-threaded
545 // Set memroy request ids to current thread
546 if (numThreads
> 1) {
547 ContextID cid
= threadContexts
[curThread
]->contextId();
549 ifetch_req
.setContext(cid
);
550 data_read_req
.setContext(cid
);
551 data_write_req
.setContext(cid
);
554 SimpleExecContext
& t_info
= *threadInfo
[curThread
];
555 SimpleThread
* thread
= t_info
.thread
;
559 for (int i
= 0; i
< width
|| locked
; ++i
) {
561 updateCycleCounters(BaseCPU::CPU_STATE_ON
);
563 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit()) {
564 checkForInterrupts();
568 // We must have just got suspended by a PC event
569 if (_status
== Idle
) {
574 Fault fault
= NoFault
;
576 TheISA::PCState pcState
= thread
->pcState();
578 bool needToFetch
= !isRomMicroPC(pcState
.microPC()) &&
581 ifetch_req
.taskId(taskId());
582 setupFetchRequest(&ifetch_req
);
583 fault
= thread
->itb
->translateAtomic(&ifetch_req
, thread
->getTC(),
587 if (fault
== NoFault
) {
588 Tick icache_latency
= 0;
589 bool icache_access
= false;
590 dcache_access
= false; // assume no dcache access
593 // This is commented out because the decoder would act like
594 // a tiny cache otherwise. It wouldn't be flushed when needed
595 // like the I cache. It should be flushed, and when that works
596 // this code should be uncommented.
597 //Fetch more instruction memory if necessary
598 //if (decoder.needMoreBytes())
600 icache_access
= true;
601 Packet ifetch_pkt
= Packet(&ifetch_req
, MemCmd::ReadReq
);
602 ifetch_pkt
.dataStatic(&inst
);
604 if (fastmem
&& system
->isMemAddr(ifetch_pkt
.getAddr()))
605 system
->getPhysMem().access(&ifetch_pkt
);
607 icache_latency
= icachePort
.sendAtomic(&ifetch_pkt
);
609 assert(!ifetch_pkt
.isError());
611 // ifetch_req is initialized to read the instruction directly
612 // into the CPU object's inst field.
618 Tick stall_ticks
= 0;
620 fault
= curStaticInst
->execute(&t_info
, traceData
);
622 // keep an instruction count
623 if (fault
== NoFault
) {
625 ppCommit
->notify(std::make_pair(thread
, curStaticInst
));
627 else if (traceData
&& !DTRACE(ExecFaulting
)) {
632 if (dynamic_pointer_cast
<SyscallRetryFault
>(fault
)) {
633 // Retry execution of system calls after a delay.
634 // Prevents immediate re-execution since conditions which
635 // caused the retry are unlikely to change every tick.
636 stall_ticks
+= clockEdge(syscallRetryLatency
) - curTick();
642 // @todo remove me after debugging with legion done
643 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
644 curStaticInst
->isFirstMicroop()))
647 if (simulate_inst_stalls
&& icache_access
)
648 stall_ticks
+= icache_latency
;
650 if (simulate_data_stalls
&& dcache_access
)
651 stall_ticks
+= dcache_latency
;
654 // the atomic cpu does its accounting in ticks, so
655 // keep counting in ticks but round to the clock
657 latency
+= divCeil(stall_ticks
, clockPeriod()) *
662 if (fault
!= NoFault
|| !t_info
.stayAtPC
)
666 if (tryCompleteDrain())
669 // instruction takes at least one cycle
670 if (latency
< clockPeriod())
671 latency
= clockPeriod();
674 reschedule(tickEvent
, curTick() + latency
, true);
678 AtomicSimpleCPU::regProbePoints()
680 BaseCPU::regProbePoints();
682 ppCommit
= new ProbePointArg
<pair
<SimpleThread
*, const StaticInstPtr
>>
683 (getProbeManager(), "Commit");
687 AtomicSimpleCPU::printAddr(Addr a
)
689 dcachePort
.printAddr(a
);
692 ////////////////////////////////////////////////////////////////////////
694 // AtomicSimpleCPU Simulation Object
697 AtomicSimpleCPUParams::create()
699 return new AtomicSimpleCPU(this);