src/cpu/simple/atomic.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #include "arch/locked_mem.hh"
  32 #include "arch/mmaped_ipr.hh"
  33 #include "arch/utility.hh"
  34 #include "base/bigint.hh"
  35 #include "cpu/exetrace.hh"
  36 #include "cpu/simple/atomic.hh"
  37 #include "mem/packet.hh"
  38 #include "mem/packet_access.hh"
  39 #include "params/AtomicSimpleCPU.hh"
  40 #include "sim/system.hh"
  41
  42 using namespace std;
  43 using namespace TheISA;
  44
  45 AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
  46     : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
  47 {
  48 }
  49
  50
  51 void
  52 AtomicSimpleCPU::TickEvent::process()
  53 {
  54     cpu->tick();
  55 }
  56
  57 const char *
  58 AtomicSimpleCPU::TickEvent::description()
  59 {
  60     return "AtomicSimpleCPU tick";
  61 }
  62
  63 Port *
  64 AtomicSimpleCPU::getPort(const std::string &if_name, int idx)
  65 {
  66     if (if_name == "dcache_port")
  67         return &dcachePort;
  68     else if (if_name == "icache_port")
  69         return &icachePort;
  70     else if (if_name == "physmem_port") {
  71         hasPhysMemPort = true;
  72         return &physmemPort;
  73     }
  74     else
  75         panic("No Such Port\n");
  76 }
  77
  78 void
  79 AtomicSimpleCPU::init()
  80 {
  81     BaseCPU::init();
  82 #if FULL_SYSTEM
  83     for (int i = 0; i < threadContexts.size(); ++i) {
  84         ThreadContext *tc = threadContexts[i];
  85
  86         // initialize CPU, including PC
  87         TheISA::initCPU(tc, tc->readCpuId());
  88     }
  89 #endif
  90     if (hasPhysMemPort) {
  91         bool snoop = false;
  92         AddrRangeList pmAddrList;
  93         physmemPort.getPeerAddressRanges(pmAddrList, snoop);
  94         physMemAddr = *pmAddrList.begin();
  95     }
  96 }
  97
  98 bool
  99 AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt)
 100 {
 101     panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
 102     return true;
 103 }
 104
 105 Tick
 106 AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
 107 {
 108     //Snooping a coherence request, just return
 109     return 0;
 110 }
 111
 112 void
 113 AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
 114 {
 115     //No internal storage to update, just return
 116     return;
 117 }
 118
 119 void
 120 AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
 121 {
 122     if (status == RangeChange) {
 123         if (!snoopRangeSent) {
 124             snoopRangeSent = true;
 125             sendStatusChange(Port::RangeChange);
 126         }
 127         return;
 128     }
 129
 130     panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
 131 }
 132
 133 void
 134 AtomicSimpleCPU::CpuPort::recvRetry()
 135 {
 136     panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
 137 }
 138
 139 void
 140 AtomicSimpleCPU::DcachePort::setPeer(Port *port)
 141 {
 142     Port::setPeer(port);
 143
 144 #if FULL_SYSTEM
 145     // Update the ThreadContext's memory ports (Functional/Virtual
 146     // Ports)
 147     cpu->tcBase()->connectMemPorts();
 148 #endif
 149 }
 150
 151 AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
 152     : BaseSimpleCPU(p), tickEvent(this),
 153       width(p->width), simulate_stalls(p->simulate_stalls),
 154       icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
 155       physmemPort(name() + "-iport", this), hasPhysMemPort(false)
 156 {
 157     _status = Idle;
 158
 159     icachePort.snoopRangeSent = false;
 160     dcachePort.snoopRangeSent = false;
 161
 162     ifetch_req.setThreadContext(p->cpu_id, 0); // Add thread ID if we add MT
 163     data_read_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
 164     data_write_req.setThreadContext(p->cpu_id, 0); // Add thread ID here too
 165 }
 166
 167
 168 AtomicSimpleCPU::~AtomicSimpleCPU()
 169 {
 170 }
 171
 172 void
 173 AtomicSimpleCPU::serialize(ostream &os)
 174 {
 175     SimObject::State so_state = SimObject::getState();
 176     SERIALIZE_ENUM(so_state);
 177     Status _status = status();
 178     SERIALIZE_ENUM(_status);
 179     BaseSimpleCPU::serialize(os);
 180     nameOut(os, csprintf("%s.tickEvent", name()));
 181     tickEvent.serialize(os);
 182 }
 183
 184 void
 185 AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 186 {
 187     SimObject::State so_state;
 188     UNSERIALIZE_ENUM(so_state);
 189     UNSERIALIZE_ENUM(_status);
 190     BaseSimpleCPU::unserialize(cp, section);
 191     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
 192 }
 193
 194 void
 195 AtomicSimpleCPU::resume()
 196 {
 197     DPRINTF(SimpleCPU, "Resume\n");
 198     if (_status != SwitchedOut && _status != Idle) {
 199         assert(system->getMemoryMode() == Enums::atomic);
 200
 201         changeState(SimObject::Running);
 202         if (thread->status() == ThreadContext::Active) {
 203             if (!tickEvent.scheduled()) {
 204                 tickEvent.schedule(nextCycle());
 205             }
 206         }
 207     }
 208 }
 209
 210 void
 211 AtomicSimpleCPU::switchOut()
 212 {
 213     assert(status() == Running || status() == Idle);
 214     _status = SwitchedOut;
 215
 216     tickEvent.squash();
 217 }
 218
 219
 220 void
 221 AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 222 {
 223     BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
 224
 225     assert(!tickEvent.scheduled());
 226
 227     // if any of this CPU's ThreadContexts are active, mark the CPU as
 228     // running and schedule its tick event.
 229     for (int i = 0; i < threadContexts.size(); ++i) {
 230         ThreadContext *tc = threadContexts[i];
 231         if (tc->status() == ThreadContext::Active && _status != Running) {
 232             _status = Running;
 233             tickEvent.schedule(nextCycle());
 234             break;
 235         }
 236     }
 237     if (_status != Running) {
 238         _status = Idle;
 239     }
 240 }
 241
 242
 243 void
 244 AtomicSimpleCPU::activateContext(int thread_num, int delay)
 245 {
 246     DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
 247
 248     assert(thread_num == 0);
 249     assert(thread);
 250
 251     assert(_status == Idle);
 252     assert(!tickEvent.scheduled());
 253
 254     notIdleFraction++;
 255
 256     //Make sure ticks are still on multiples of cycles
 257     tickEvent.schedule(nextCycle(curTick + cycles(delay)));
 258     _status = Running;
 259 }
 260
 261
 262 void
 263 AtomicSimpleCPU::suspendContext(int thread_num)
 264 {
 265     DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
 266
 267     assert(thread_num == 0);
 268     assert(thread);
 269
 270     assert(_status == Running);
 271
 272     // tick event may not be scheduled if this gets called from inside
 273     // an instruction's execution, e.g. "quiesce"
 274     if (tickEvent.scheduled())
 275         tickEvent.deschedule();
 276
 277     notIdleFraction--;
 278     _status = Idle;
 279 }
 280
 281
 282 template <class T>
 283 Fault
 284 AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
 285 {
 286     // use the CPU's statically allocated read request and packet objects
 287     Request *req = &data_read_req;
 288     req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 289
 290     if (traceData) {
 291         traceData->setAddr(addr);
 292     }
 293
 294     // translate to physical address
 295     Fault fault = thread->translateDataReadReq(req);
 296
 297     // Now do the access.
 298     if (fault == NoFault) {
 299         Packet pkt =
 300             Packet(req,
 301                    req->isLocked() ? MemCmd::LoadLockedReq : MemCmd::ReadReq,
 302                    Packet::Broadcast);
 303         pkt.dataStatic(&data);
 304
 305         if (req->isMmapedIpr())
 306             dcache_latency = TheISA::handleIprRead(thread->getTC(), &pkt);
 307         else {
 308             if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
 309                 dcache_latency = physmemPort.sendAtomic(&pkt);
 310             else
 311                 dcache_latency = dcachePort.sendAtomic(&pkt);
 312         }
 313         dcache_access = true;
 314         assert(!pkt.isError());
 315
 316         data = gtoh(data);
 317
 318         if (req->isLocked()) {
 319             TheISA::handleLockedRead(thread, req);
 320         }
 321     }
 322
 323     // This will need a new way to tell if it has a dcache attached.
 324     if (req->isUncacheable())
 325         recordEvent("Uncached Read");
 326
 327     return fault;
 328 }
 329
 330 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 331
 332 template
 333 Fault
 334 AtomicSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
 335
 336 template
 337 Fault
 338 AtomicSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
 339
 340 template
 341 Fault
 342 AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
 343
 344 template
 345 Fault
 346 AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
 347
 348 template
 349 Fault
 350 AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
 351
 352 template
 353 Fault
 354 AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
 355
 356 #endif //DOXYGEN_SHOULD_SKIP_THIS
 357
 358 template<>
 359 Fault
 360 AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
 361 {
 362     return read(addr, *(uint64_t*)&data, flags);
 363 }
 364
 365 template<>
 366 Fault
 367 AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
 368 {
 369     return read(addr, *(uint32_t*)&data, flags);
 370 }
 371
 372
 373 template<>
 374 Fault
 375 AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
 376 {
 377     return read(addr, (uint32_t&)data, flags);
 378 }
 379
 380
 381 template <class T>
 382 Fault
 383 AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 384 {
 385     // use the CPU's statically allocated write request and packet objects
 386     Request *req = &data_write_req;
 387     req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 388
 389     if (traceData) {
 390         traceData->setAddr(addr);
 391     }
 392
 393     // translate to physical address
 394     Fault fault = thread->translateDataWriteReq(req);
 395
 396     // Now do the access.
 397     if (fault == NoFault) {
 398         MemCmd cmd = MemCmd::WriteReq; // default
 399         bool do_access = true;  // flag to suppress cache access
 400
 401         if (req->isLocked()) {
 402             cmd = MemCmd::StoreCondReq;
 403             do_access = TheISA::handleLockedWrite(thread, req);
 404         } else if (req->isSwap()) {
 405             cmd = MemCmd::SwapReq;
 406             if (req->isCondSwap()) {
 407                 assert(res);
 408                 req->setExtraData(*res);
 409             }
 410         }
 411
 412         if (do_access) {
 413             Packet pkt = Packet(req, cmd, Packet::Broadcast);
 414             pkt.dataStatic(&data);
 415
 416             if (req->isMmapedIpr()) {
 417                 dcache_latency = TheISA::handleIprWrite(thread->getTC(), &pkt);
 418             } else {
 419                 data = htog(data);
 420                 if (hasPhysMemPort && pkt.getAddr() == physMemAddr)
 421                     dcache_latency = physmemPort.sendAtomic(&pkt);
 422                 else
 423                     dcache_latency = dcachePort.sendAtomic(&pkt);
 424             }
 425             dcache_access = true;
 426             assert(!pkt.isError());
 427
 428             if (req->isSwap()) {
 429                 assert(res);
 430                 *res = pkt.get<T>();
 431             }
 432         }
 433
 434         if (res && !req->isSwap()) {
 435             *res = req->getExtraData();
 436         }
 437     }
 438
 439     // This will need a new way to tell if it's hooked up to a cache or not.
 440     if (req->isUncacheable())
 441         recordEvent("Uncached Write");
 442
 443     // If the write needs to have a fault on the access, consider calling
 444     // changeStatus() and changing it to "bad addr write" or something.
 445     return fault;
 446 }
 447
 448
 449 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 450
 451 template
 452 Fault
 453 AtomicSimpleCPU::write(Twin32_t data, Addr addr,
 454                        unsigned flags, uint64_t *res);
 455
 456 template
 457 Fault
 458 AtomicSimpleCPU::write(Twin64_t data, Addr addr,
 459                        unsigned flags, uint64_t *res);
 460
 461 template
 462 Fault
 463 AtomicSimpleCPU::write(uint64_t data, Addr addr,
 464                        unsigned flags, uint64_t *res);
 465
 466 template
 467 Fault
 468 AtomicSimpleCPU::write(uint32_t data, Addr addr,
 469                        unsigned flags, uint64_t *res);
 470
 471 template
 472 Fault
 473 AtomicSimpleCPU::write(uint16_t data, Addr addr,
 474                        unsigned flags, uint64_t *res);
 475
 476 template
 477 Fault
 478 AtomicSimpleCPU::write(uint8_t data, Addr addr,
 479                        unsigned flags, uint64_t *res);
 480
 481 #endif //DOXYGEN_SHOULD_SKIP_THIS
 482
 483 template<>
 484 Fault
 485 AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
 486 {
 487     return write(*(uint64_t*)&data, addr, flags, res);
 488 }
 489
 490 template<>
 491 Fault
 492 AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
 493 {
 494     return write(*(uint32_t*)&data, addr, flags, res);
 495 }
 496
 497
 498 template<>
 499 Fault
 500 AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 501 {
 502     return write((uint32_t)data, addr, flags, res);
 503 }
 504
 505
 506 void
 507 AtomicSimpleCPU::tick()
 508 {
 509     DPRINTF(SimpleCPU, "Tick\n");
 510
 511     Tick latency = cycles(1); // instruction takes one cycle by default
 512
 513     for (int i = 0; i < width; ++i) {
 514         numCycles++;
 515
 516         if (!curStaticInst || !curStaticInst->isDelayedCommit())
 517             checkForInterrupts();
 518
 519         Fault fault = setupFetchRequest(&ifetch_req);
 520
 521         if (fault == NoFault) {
 522             Tick icache_latency = 0;
 523             bool icache_access = false;
 524             dcache_access = false; // assume no dcache access
 525
 526             //Fetch more instruction memory if necessary
 527             //if(predecoder.needMoreBytes())
 528             //{
 529                 icache_access = true;
 530                 Packet ifetch_pkt = Packet(&ifetch_req, MemCmd::ReadReq,
 531                                            Packet::Broadcast);
 532                 ifetch_pkt.dataStatic(&inst);
 533
 534                 if (hasPhysMemPort && ifetch_pkt.getAddr() == physMemAddr)
 535                     icache_latency = physmemPort.sendAtomic(&ifetch_pkt);
 536                 else
 537                     icache_latency = icachePort.sendAtomic(&ifetch_pkt);
 538
 539
 540                 // ifetch_req is initialized to read the instruction directly
 541                 // into the CPU object's inst field.
 542             //}
 543
 544             preExecute();
 545
 546             if(curStaticInst)
 547             {
 548                 fault = curStaticInst->execute(this, traceData);
 549                 postExecute();
 550             }
 551
 552             // @todo remove me after debugging with legion done
 553             if (curStaticInst && (!curStaticInst->isMicroop() ||
 554                         curStaticInst->isFirstMicroop()))
 555                 instCnt++;
 556
 557             if (simulate_stalls) {
 558                 Tick icache_stall =
 559                     icache_access ? icache_latency - cycles(1) : 0;
 560                 Tick dcache_stall =
 561                     dcache_access ? dcache_latency - cycles(1) : 0;
 562                 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
 563                 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
 564                     latency += cycles(stall_cycles+1);
 565                 else
 566                     latency += cycles(stall_cycles);
 567             }
 568
 569         }
 570         if(fault != NoFault || !stayAtPC)
 571             advancePC(fault);
 572     }
 573
 574     if (_status != Idle)
 575         tickEvent.schedule(curTick + latency);
 576 }
 577
 578
 579 ////////////////////////////////////////////////////////////////////////
 580 //
 581 //  AtomicSimpleCPU Simulation Object
 582 //
 583 AtomicSimpleCPU *
 584 AtomicSimpleCPUParams::create()
 585 {
 586     AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
 587     params->name = name;
 588     params->numberOfThreads = 1;
 589     params->max_insts_any_thread = max_insts_any_thread;
 590     params->max_insts_all_threads = max_insts_all_threads;
 591     params->max_loads_any_thread = max_loads_any_thread;
 592     params->max_loads_all_threads = max_loads_all_threads;
 593     params->progress_interval = progress_interval;
 594     params->deferRegistration = defer_registration;
 595     params->phase = phase;
 596     params->clock = clock;
 597     params->functionTrace = function_trace;
 598     params->functionTraceStart = function_trace_start;
 599     params->width = width;
 600     params->simulate_stalls = simulate_stalls;
 601     params->system = system;
 602     params->cpu_id = cpu_id;
 603     params->tracer = tracer;
 604
 605     params->itb = itb;
 606     params->dtb = dtb;
 607 #if FULL_SYSTEM
 608     params->profile = profile;
 609     params->do_quiesce = do_quiesce;
 610     params->do_checkpoint_insts = do_checkpoint_insts;
 611     params->do_statistics_insts = do_statistics_insts;
 612 #else
 613     if (workload.size() != 1)
 614         panic("only one workload allowed");
 615     params->process = workload[0];
 616 #endif
 617
 618     AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
 619     return cpu;
 620 }