2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/locked_mem.hh"
32 #include "arch/mmaped_ipr.hh"
33 #include "arch/utility.hh"
34 #include "base/bigint.hh"
35 #include "cpu/exetrace.hh"
36 #include "cpu/simple/atomic.hh"
37 #include "mem/packet.hh"
38 #include "mem/packet_access.hh"
39 #include "params/AtomicSimpleCPU.hh"
40 #include "sim/system.hh"
43 using namespace TheISA
;
45 AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU
*c
)
46 : Event(&mainEventQueue
, CPU_Tick_Pri
), cpu(c
)
52 AtomicSimpleCPU::TickEvent::process()
58 AtomicSimpleCPU::TickEvent::description()
60 return "AtomicSimpleCPU tick";
64 AtomicSimpleCPU::getPort(const std::string
&if_name
, int idx
)
66 if (if_name
== "dcache_port")
68 else if (if_name
== "icache_port")
70 else if (if_name
== "physmem_port") {
71 hasPhysMemPort
= true;
75 panic("No Such Port\n");
79 AtomicSimpleCPU::init()
82 cpuId
= tc
->readCpuId();
84 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
85 ThreadContext
*tc
= threadContexts
[i
];
87 // initialize CPU, including PC
88 TheISA::initCPU(tc
, cpuId
);
93 AddrRangeList pmAddrList
;
94 physmemPort
.getPeerAddressRanges(pmAddrList
, snoop
);
95 physMemAddr
= *pmAddrList
.begin();
97 ifetch_req
.setThreadContext(cpuId
, 0); // Add thread ID if we add MT
98 data_read_req
.setThreadContext(cpuId
, 0); // Add thread ID here too
99 data_write_req
.setThreadContext(cpuId
, 0); // Add thread ID here too
103 AtomicSimpleCPU::CpuPort::recvTiming(PacketPtr pkt
)
105 panic("AtomicSimpleCPU doesn't expect recvTiming callback!");
110 AtomicSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt
)
112 //Snooping a coherence request, just return
117 AtomicSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt
)
119 //No internal storage to update, just return
124 AtomicSimpleCPU::CpuPort::recvStatusChange(Status status
)
126 if (status
== RangeChange
) {
127 if (!snoopRangeSent
) {
128 snoopRangeSent
= true;
129 sendStatusChange(Port::RangeChange
);
134 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
138 AtomicSimpleCPU::CpuPort::recvRetry()
140 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
144 AtomicSimpleCPU::DcachePort::setPeer(Port
*port
)
149 // Update the ThreadContext's memory ports (Functional/Virtual
151 cpu
->tcBase()->connectMemPorts();
155 AtomicSimpleCPU::AtomicSimpleCPU(Params
*p
)
156 : BaseSimpleCPU(p
), tickEvent(this),
157 width(p
->width
), simulate_stalls(p
->simulate_stalls
),
158 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this),
159 physmemPort(name() + "-iport", this), hasPhysMemPort(false)
163 icachePort
.snoopRangeSent
= false;
164 dcachePort
.snoopRangeSent
= false;
169 AtomicSimpleCPU::~AtomicSimpleCPU()
174 AtomicSimpleCPU::serialize(ostream
&os
)
176 SimObject::State so_state
= SimObject::getState();
177 SERIALIZE_ENUM(so_state
);
178 Status _status
= status();
179 SERIALIZE_ENUM(_status
);
180 BaseSimpleCPU::serialize(os
);
181 nameOut(os
, csprintf("%s.tickEvent", name()));
182 tickEvent
.serialize(os
);
186 AtomicSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
188 SimObject::State so_state
;
189 UNSERIALIZE_ENUM(so_state
);
190 UNSERIALIZE_ENUM(_status
);
191 BaseSimpleCPU::unserialize(cp
, section
);
192 tickEvent
.unserialize(cp
, csprintf("%s.tickEvent", section
));
196 AtomicSimpleCPU::resume()
198 if (_status
== Idle
|| _status
== SwitchedOut
)
201 DPRINTF(SimpleCPU
, "Resume\n");
202 assert(system
->getMemoryMode() == Enums::atomic
);
204 changeState(SimObject::Running
);
205 if (thread
->status() == ThreadContext::Active
) {
206 if (!tickEvent
.scheduled()) {
207 tickEvent
.schedule(nextCycle());
213 AtomicSimpleCPU::switchOut()
215 assert(status() == Running
|| status() == Idle
);
216 _status
= SwitchedOut
;
223 AtomicSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
225 BaseCPU::takeOverFrom(oldCPU
, &icachePort
, &dcachePort
);
227 assert(!tickEvent
.scheduled());
229 // if any of this CPU's ThreadContexts are active, mark the CPU as
230 // running and schedule its tick event.
231 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
232 ThreadContext
*tc
= threadContexts
[i
];
233 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
235 tickEvent
.schedule(nextCycle());
239 if (_status
!= Running
) {
242 assert(threadContexts
.size() == 1);
243 cpuId
= tc
->readCpuId();
244 ifetch_req
.setThreadContext(cpuId
, 0); // Add thread ID if we add MT
245 data_read_req
.setThreadContext(cpuId
, 0); // Add thread ID here too
246 data_write_req
.setThreadContext(cpuId
, 0); // Add thread ID here too
251 AtomicSimpleCPU::activateContext(int thread_num
, int delay
)
253 DPRINTF(SimpleCPU
, "ActivateContext %d (%d cycles)\n", thread_num
, delay
);
255 assert(thread_num
== 0);
258 assert(_status
== Idle
);
259 assert(!tickEvent
.scheduled());
262 numCycles
+= tickToCycles(thread
->lastActivate
- thread
->lastSuspend
);
264 //Make sure ticks are still on multiples of cycles
265 tickEvent
.schedule(nextCycle(curTick
+ ticks(delay
)));
271 AtomicSimpleCPU::suspendContext(int thread_num
)
273 DPRINTF(SimpleCPU
, "SuspendContext %d\n", thread_num
);
275 assert(thread_num
== 0);
278 assert(_status
== Running
);
280 // tick event may not be scheduled if this gets called from inside
281 // an instruction's execution, e.g. "quiesce"
282 if (tickEvent
.scheduled())
283 tickEvent
.deschedule();
292 AtomicSimpleCPU::read(Addr addr
, T
&data
, unsigned flags
)
294 // use the CPU's statically allocated read request and packet objects
295 Request
*req
= &data_read_req
;
298 traceData
->setAddr(addr
);
301 //The block size of our peer.
302 int blockSize
= dcachePort
.peerBlockSize();
303 //The size of the data we're trying to read.
304 int dataSize
= sizeof(T
);
306 uint8_t * dataPtr
= (uint8_t *)&data
;
308 //The address of the second part of this access if it needs to be split
309 //across a cache line boundary.
310 Addr secondAddr
= roundDown(addr
+ dataSize
- 1, blockSize
);
312 if(secondAddr
> addr
)
313 dataSize
= secondAddr
- addr
;
318 req
->setVirt(0, addr
, dataSize
, flags
, thread
->readPC());
320 // translate to physical address
321 Fault fault
= thread
->translateDataReadReq(req
);
323 // Now do the access.
324 if (fault
== NoFault
) {
325 Packet pkt
= Packet(req
,
326 req
->isLocked() ? MemCmd::LoadLockedReq
: MemCmd::ReadReq
,
328 pkt
.dataStatic(dataPtr
);
330 if (req
->isMmapedIpr())
331 dcache_latency
+= TheISA::handleIprRead(thread
->getTC(), &pkt
);
333 if (hasPhysMemPort
&& pkt
.getAddr() == physMemAddr
)
334 dcache_latency
+= physmemPort
.sendAtomic(&pkt
);
336 dcache_latency
+= dcachePort
.sendAtomic(&pkt
);
338 dcache_access
= true;
340 assert(!pkt
.isError());
342 if (req
->isLocked()) {
343 TheISA::handleLockedRead(thread
, req
);
347 // This will need a new way to tell if it has a dcache attached.
348 if (req
->isUncacheable())
349 recordEvent("Uncached Read");
351 //If there's a fault, return it
352 if (fault
!= NoFault
)
354 //If we don't need to access a second cache line, stop now.
355 if (secondAddr
<= addr
)
362 * Set up for accessing the second cache line.
365 //Move the pointer we're reading into to the correct location.
367 //Adjust the size to get the remaining bytes.
368 dataSize
= addr
+ sizeof(T
) - secondAddr
;
369 //And access the right address.
375 AtomicSimpleCPU::translateDataReadAddr(Addr vaddr
, Addr
& paddr
,
376 int size
, unsigned flags
)
378 // use the CPU's statically allocated read request and packet objects
379 Request
*req
= &data_read_req
;
382 traceData
->setAddr(vaddr
);
385 //The block size of our peer.
386 int blockSize
= dcachePort
.peerBlockSize();
387 //The size of the data we're trying to read.
390 bool firstTimeThrough
= true;
392 //The address of the second part of this access if it needs to be split
393 //across a cache line boundary.
394 Addr secondAddr
= roundDown(vaddr
+ dataSize
- 1, blockSize
);
396 if(secondAddr
> vaddr
)
397 dataSize
= secondAddr
- vaddr
;
400 req
->setVirt(0, vaddr
, dataSize
, flags
, thread
->readPC());
402 // translate to physical address
403 Fault fault
= thread
->translateDataReadReq(req
);
405 //If there's a fault, return it
406 if (fault
!= NoFault
)
409 if (firstTimeThrough
) {
410 paddr
= req
->getPaddr();
411 firstTimeThrough
= false;
414 //If we don't need to access a second cache line, stop now.
415 if (secondAddr
<= vaddr
)
419 * Set up for accessing the second cache line.
422 //Adjust the size to get the remaining bytes.
423 dataSize
= vaddr
+ size
- secondAddr
;
424 //And access the right address.
429 #ifndef DOXYGEN_SHOULD_SKIP_THIS
433 AtomicSimpleCPU::read(Addr addr
, Twin32_t
&data
, unsigned flags
);
437 AtomicSimpleCPU::read(Addr addr
, Twin64_t
&data
, unsigned flags
);
441 AtomicSimpleCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
445 AtomicSimpleCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
449 AtomicSimpleCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
453 AtomicSimpleCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
455 #endif //DOXYGEN_SHOULD_SKIP_THIS
459 AtomicSimpleCPU::read(Addr addr
, double &data
, unsigned flags
)
461 return read(addr
, *(uint64_t*)&data
, flags
);
466 AtomicSimpleCPU::read(Addr addr
, float &data
, unsigned flags
)
468 return read(addr
, *(uint32_t*)&data
, flags
);
474 AtomicSimpleCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
476 return read(addr
, (uint32_t&)data
, flags
);
482 AtomicSimpleCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
484 // use the CPU's statically allocated write request and packet objects
485 Request
*req
= &data_write_req
;
488 traceData
->setAddr(addr
);
491 //The block size of our peer.
492 int blockSize
= dcachePort
.peerBlockSize();
493 //The size of the data we're trying to read.
494 int dataSize
= sizeof(T
);
496 uint8_t * dataPtr
= (uint8_t *)&data
;
498 //The address of the second part of this access if it needs to be split
499 //across a cache line boundary.
500 Addr secondAddr
= roundDown(addr
+ dataSize
- 1, blockSize
);
502 if(secondAddr
> addr
)
503 dataSize
= secondAddr
- addr
;
508 req
->setVirt(0, addr
, dataSize
, flags
, thread
->readPC());
510 // translate to physical address
511 Fault fault
= thread
->translateDataWriteReq(req
);
513 // Now do the access.
514 if (fault
== NoFault
) {
515 MemCmd cmd
= MemCmd::WriteReq
; // default
516 bool do_access
= true; // flag to suppress cache access
518 if (req
->isLocked()) {
519 cmd
= MemCmd::StoreCondReq
;
520 do_access
= TheISA::handleLockedWrite(thread
, req
);
521 } else if (req
->isSwap()) {
522 cmd
= MemCmd::SwapReq
;
523 if (req
->isCondSwap()) {
525 req
->setExtraData(*res
);
530 Packet pkt
= Packet(req
, cmd
, Packet::Broadcast
);
531 pkt
.dataStatic(dataPtr
);
533 if (req
->isMmapedIpr()) {
535 TheISA::handleIprWrite(thread
->getTC(), &pkt
);
537 //XXX This needs to be outside of the loop in order to
538 //work properly for cache line boundary crossing
539 //accesses in transendian simulations.
541 if (hasPhysMemPort
&& pkt
.getAddr() == physMemAddr
)
542 dcache_latency
+= physmemPort
.sendAtomic(&pkt
);
544 dcache_latency
+= dcachePort
.sendAtomic(&pkt
);
546 dcache_access
= true;
547 assert(!pkt
.isError());
555 if (res
&& !req
->isSwap()) {
556 *res
= req
->getExtraData();
560 // This will need a new way to tell if it's hooked up to a cache or not.
561 if (req
->isUncacheable())
562 recordEvent("Uncached Write");
564 //If there's a fault or we don't need to access a second cache line,
566 if (fault
!= NoFault
|| secondAddr
<= addr
)
568 // If the write needs to have a fault on the access, consider
569 // calling changeStatus() and changing it to "bad addr write"
575 * Set up for accessing the second cache line.
578 //Move the pointer we're reading into to the correct location.
580 //Adjust the size to get the remaining bytes.
581 dataSize
= addr
+ sizeof(T
) - secondAddr
;
582 //And access the right address.
588 AtomicSimpleCPU::translateDataWriteAddr(Addr vaddr
, Addr
&paddr
,
589 int size
, unsigned flags
)
591 // use the CPU's statically allocated write request and packet objects
592 Request
*req
= &data_write_req
;
595 traceData
->setAddr(vaddr
);
598 //The block size of our peer.
599 int blockSize
= dcachePort
.peerBlockSize();
601 //The address of the second part of this access if it needs to be split
602 //across a cache line boundary.
603 Addr secondAddr
= roundDown(vaddr
+ size
- 1, blockSize
);
605 //The size of the data we're trying to read.
608 bool firstTimeThrough
= true;
610 if(secondAddr
> vaddr
)
611 dataSize
= secondAddr
- vaddr
;
616 req
->setVirt(0, vaddr
, dataSize
, flags
, thread
->readPC());
618 // translate to physical address
619 Fault fault
= thread
->translateDataWriteReq(req
);
621 //If there's a fault or we don't need to access a second cache line,
623 if (fault
!= NoFault
)
626 if (firstTimeThrough
) {
627 paddr
= req
->getPaddr();
628 firstTimeThrough
= false;
631 if (secondAddr
<= vaddr
)
635 * Set up for accessing the second cache line.
638 //Adjust the size to get the remaining bytes.
639 dataSize
= vaddr
+ size
- secondAddr
;
640 //And access the right address.
646 #ifndef DOXYGEN_SHOULD_SKIP_THIS
650 AtomicSimpleCPU::write(Twin32_t data
, Addr addr
,
651 unsigned flags
, uint64_t *res
);
655 AtomicSimpleCPU::write(Twin64_t data
, Addr addr
,
656 unsigned flags
, uint64_t *res
);
660 AtomicSimpleCPU::write(uint64_t data
, Addr addr
,
661 unsigned flags
, uint64_t *res
);
665 AtomicSimpleCPU::write(uint32_t data
, Addr addr
,
666 unsigned flags
, uint64_t *res
);
670 AtomicSimpleCPU::write(uint16_t data
, Addr addr
,
671 unsigned flags
, uint64_t *res
);
675 AtomicSimpleCPU::write(uint8_t data
, Addr addr
,
676 unsigned flags
, uint64_t *res
);
678 #endif //DOXYGEN_SHOULD_SKIP_THIS
682 AtomicSimpleCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
684 return write(*(uint64_t*)&data
, addr
, flags
, res
);
689 AtomicSimpleCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
691 return write(*(uint32_t*)&data
, addr
, flags
, res
);
697 AtomicSimpleCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
699 return write((uint32_t)data
, addr
, flags
, res
);
704 AtomicSimpleCPU::tick()
706 DPRINTF(SimpleCPU
, "Tick\n");
708 Tick latency
= ticks(1); // instruction takes one cycle by default
710 for (int i
= 0; i
< width
; ++i
) {
713 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit())
714 checkForInterrupts();
716 Fault fault
= setupFetchRequest(&ifetch_req
);
718 if (fault
== NoFault
) {
719 Tick icache_latency
= 0;
720 bool icache_access
= false;
721 dcache_access
= false; // assume no dcache access
723 //Fetch more instruction memory if necessary
724 //if(predecoder.needMoreBytes())
726 icache_access
= true;
727 Packet ifetch_pkt
= Packet(&ifetch_req
, MemCmd::ReadReq
,
729 ifetch_pkt
.dataStatic(&inst
);
731 if (hasPhysMemPort
&& ifetch_pkt
.getAddr() == physMemAddr
)
732 icache_latency
= physmemPort
.sendAtomic(&ifetch_pkt
);
734 icache_latency
= icachePort
.sendAtomic(&ifetch_pkt
);
736 assert(!ifetch_pkt
.isError());
738 // ifetch_req is initialized to read the instruction directly
739 // into the CPU object's inst field.
745 fault
= curStaticInst
->execute(this, traceData
);
747 // keep an instruction count
748 if (fault
== NoFault
)
750 else if (traceData
) {
751 // If there was a fault, we should trace this instruction.
759 // @todo remove me after debugging with legion done
760 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
761 curStaticInst
->isFirstMicroop()))
764 if (simulate_stalls
) {
766 icache_access
? icache_latency
- ticks(1) : 0;
768 dcache_access
? dcache_latency
- ticks(1) : 0;
769 Tick stall_cycles
= (icache_stall
+ dcache_stall
) / ticks(1);
770 if (ticks(stall_cycles
) < (icache_stall
+ dcache_stall
))
771 latency
+= ticks(stall_cycles
+1);
773 latency
+= ticks(stall_cycles
);
777 if(fault
!= NoFault
|| !stayAtPC
)
782 tickEvent
.schedule(curTick
+ latency
);
786 ////////////////////////////////////////////////////////////////////////
788 // AtomicSimpleCPU Simulation Object
791 AtomicSimpleCPUParams::create()
793 AtomicSimpleCPU::Params
*params
= new AtomicSimpleCPU::Params();
795 params
->numberOfThreads
= 1;
796 params
->max_insts_any_thread
= max_insts_any_thread
;
797 params
->max_insts_all_threads
= max_insts_all_threads
;
798 params
->max_loads_any_thread
= max_loads_any_thread
;
799 params
->max_loads_all_threads
= max_loads_all_threads
;
800 params
->progress_interval
= progress_interval
;
801 params
->deferRegistration
= defer_registration
;
802 params
->phase
= phase
;
803 params
->clock
= clock
;
804 params
->functionTrace
= function_trace
;
805 params
->functionTraceStart
= function_trace_start
;
806 params
->width
= width
;
807 params
->simulate_stalls
= simulate_stalls
;
808 params
->system
= system
;
809 params
->cpu_id
= cpu_id
;
810 params
->tracer
= tracer
;
815 params
->profile
= profile
;
816 params
->do_quiesce
= do_quiesce
;
817 params
->do_checkpoint_insts
= do_checkpoint_insts
;
818 params
->do_statistics_insts
= do_statistics_insts
;
820 if (workload
.size() != 1)
821 panic("only one workload allowed");
822 params
->process
= workload
[0];
825 AtomicSimpleCPU
*cpu
= new AtomicSimpleCPU(params
);