src/cpu/simple/atomic.cc

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Steve Reinhardt
  29  */
  30
  31 #include "arch/utility.hh"
  32 #include "cpu/exetrace.hh"
  33 #include "cpu/simple/atomic.hh"
  34 #include "mem/packet_impl.hh"
  35 #include "sim/builder.hh"
  36
  37 using namespace std;
  38 using namespace TheISA;
  39
  40 AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU *c)
  41     : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
  42 {
  43 }
  44
  45
  46 void
  47 AtomicSimpleCPU::TickEvent::process()
  48 {
  49     cpu->tick();
  50 }
  51
  52 const char *
  53 AtomicSimpleCPU::TickEvent::description()
  54 {
  55     return "AtomicSimpleCPU tick event";
  56 }
  57
  58
  59 void
  60 AtomicSimpleCPU::init()
  61 {
  62     //Create Memory Ports (conect them up)
  63     Port *mem_dport = mem->getPort("");
  64     dcachePort.setPeer(mem_dport);
  65     mem_dport->setPeer(&dcachePort);
  66
  67     Port *mem_iport = mem->getPort("");
  68     icachePort.setPeer(mem_iport);
  69     mem_iport->setPeer(&icachePort);
  70
  71     BaseCPU::init();
  72 #if FULL_SYSTEM
  73     for (int i = 0; i < threadContexts.size(); ++i) {
  74         ThreadContext *tc = threadContexts[i];
  75
  76         // initialize CPU, including PC
  77         TheISA::initCPU(tc, tc->readCpuId());
  78     }
  79 #endif
  80 }
  81
  82 bool
  83 AtomicSimpleCPU::CpuPort::recvTiming(Packet *pkt)
  84 {
  85     panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
  86     return true;
  87 }
  88
  89 Tick
  90 AtomicSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
  91 {
  92     panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
  93     return curTick;
  94 }
  95
  96 void
  97 AtomicSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
  98 {
  99     panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
 100 }
 101
 102 void
 103 AtomicSimpleCPU::CpuPort::recvStatusChange(Status status)
 104 {
 105     if (status == RangeChange)
 106         return;
 107
 108     panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
 109 }
 110
 111 void
 112 AtomicSimpleCPU::CpuPort::recvRetry()
 113 {
 114     panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
 115 }
 116
 117
 118 AtomicSimpleCPU::AtomicSimpleCPU(Params *p)
 119     : BaseSimpleCPU(p), tickEvent(this),
 120       width(p->width), simulate_stalls(p->simulate_stalls),
 121       icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
 122 {
 123     _status = Idle;
 124
 125     // @todo fix me and get the real cpu id & thread number!!!
 126     ifetch_req = new Request();
 127     ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
 128     ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
 129     ifetch_pkt->dataStatic(&inst);
 130
 131     data_read_req = new Request();
 132     data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
 133     data_read_pkt = new Packet(data_read_req, Packet::ReadReq,
 134                                Packet::Broadcast);
 135     data_read_pkt->dataStatic(&dataReg);
 136
 137     data_write_req = new Request();
 138     data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
 139     data_write_pkt = new Packet(data_write_req, Packet::WriteReq,
 140                                 Packet::Broadcast);
 141 }
 142
 143
 144 AtomicSimpleCPU::~AtomicSimpleCPU()
 145 {
 146 }
 147
 148 void
 149 AtomicSimpleCPU::serialize(ostream &os)
 150 {
 151     SERIALIZE_ENUM(_status);
 152     BaseSimpleCPU::serialize(os);
 153     nameOut(os, csprintf("%s.tickEvent", name()));
 154     tickEvent.serialize(os);
 155 }
 156
 157 void
 158 AtomicSimpleCPU::unserialize(Checkpoint *cp, const string &section)
 159 {
 160     UNSERIALIZE_ENUM(_status);
 161     BaseSimpleCPU::unserialize(cp, section);
 162     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
 163 }
 164
 165 void
 166 AtomicSimpleCPU::switchOut()
 167 {
 168     assert(status() == Running || status() == Idle);
 169     _status = SwitchedOut;
 170
 171     tickEvent.squash();
 172 }
 173
 174
 175 void
 176 AtomicSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 177 {
 178     BaseCPU::takeOverFrom(oldCPU);
 179
 180     assert(!tickEvent.scheduled());
 181
 182     // if any of this CPU's ThreadContexts are active, mark the CPU as
 183     // running and schedule its tick event.
 184     for (int i = 0; i < threadContexts.size(); ++i) {
 185         ThreadContext *tc = threadContexts[i];
 186         if (tc->status() == ThreadContext::Active && _status != Running) {
 187             _status = Running;
 188             tickEvent.schedule(curTick);
 189             break;
 190         }
 191     }
 192 }
 193
 194
 195 void
 196 AtomicSimpleCPU::activateContext(int thread_num, int delay)
 197 {
 198     assert(thread_num == 0);
 199     assert(thread);
 200
 201     assert(_status == Idle);
 202     assert(!tickEvent.scheduled());
 203
 204     notIdleFraction++;
 205     tickEvent.schedule(curTick + cycles(delay));
 206     _status = Running;
 207 }
 208
 209
 210 void
 211 AtomicSimpleCPU::suspendContext(int thread_num)
 212 {
 213     assert(thread_num == 0);
 214     assert(thread);
 215
 216     assert(_status == Running);
 217
 218     // tick event may not be scheduled if this gets called from inside
 219     // an instruction's execution, e.g. "quiesce"
 220     if (tickEvent.scheduled())
 221         tickEvent.deschedule();
 222
 223     notIdleFraction--;
 224     _status = Idle;
 225 }
 226
 227
 228 template <class T>
 229 Fault
 230 AtomicSimpleCPU::read(Addr addr, T &data, unsigned flags)
 231 {
 232     data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 233
 234     if (traceData) {
 235         traceData->setAddr(addr);
 236     }
 237
 238     // translate to physical address
 239     Fault fault = thread->translateDataReadReq(data_read_req);
 240
 241     // Now do the access.
 242     if (fault == NoFault) {
 243         data_read_pkt->reinitFromRequest();
 244
 245         dcache_latency = dcachePort.sendAtomic(data_read_pkt);
 246         dcache_access = true;
 247
 248         assert(data_read_pkt->result == Packet::Success);
 249         data = data_read_pkt->get<T>();
 250
 251     }
 252
 253     // This will need a new way to tell if it has a dcache attached.
 254     if (data_read_req->getFlags() & UNCACHEABLE)
 255         recordEvent("Uncached Read");
 256
 257     return fault;
 258 }
 259
 260 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 261
 262 template
 263 Fault
 264 AtomicSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
 265
 266 template
 267 Fault
 268 AtomicSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
 269
 270 template
 271 Fault
 272 AtomicSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
 273
 274 template
 275 Fault
 276 AtomicSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
 277
 278 #endif //DOXYGEN_SHOULD_SKIP_THIS
 279
 280 template<>
 281 Fault
 282 AtomicSimpleCPU::read(Addr addr, double &data, unsigned flags)
 283 {
 284     return read(addr, *(uint64_t*)&data, flags);
 285 }
 286
 287 template<>
 288 Fault
 289 AtomicSimpleCPU::read(Addr addr, float &data, unsigned flags)
 290 {
 291     return read(addr, *(uint32_t*)&data, flags);
 292 }
 293
 294
 295 template<>
 296 Fault
 297 AtomicSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
 298 {
 299     return read(addr, (uint32_t&)data, flags);
 300 }
 301
 302
 303 template <class T>
 304 Fault
 305 AtomicSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 306 {
 307     data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
 308
 309     if (traceData) {
 310         traceData->setAddr(addr);
 311     }
 312
 313     // translate to physical address
 314     Fault fault = thread->translateDataWriteReq(data_write_req);
 315
 316     // Now do the access.
 317     if (fault == NoFault) {
 318         data = htog(data);
 319         data_write_pkt->reinitFromRequest();
 320         data_write_pkt->dataStatic(&data);
 321
 322         dcache_latency = dcachePort.sendAtomic(data_write_pkt);
 323         dcache_access = true;
 324
 325         assert(data_write_pkt->result == Packet::Success);
 326
 327         if (res && data_write_req->getFlags() & LOCKED) {
 328             *res = data_write_req->getScResult();
 329         }
 330     }
 331
 332     // This will need a new way to tell if it's hooked up to a cache or not.
 333     if (data_write_req->getFlags() & UNCACHEABLE)
 334         recordEvent("Uncached Write");
 335
 336     // If the write needs to have a fault on the access, consider calling
 337     // changeStatus() and changing it to "bad addr write" or something.
 338     return fault;
 339 }
 340
 341
 342 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 343 template
 344 Fault
 345 AtomicSimpleCPU::write(uint64_t data, Addr addr,
 346                        unsigned flags, uint64_t *res);
 347
 348 template
 349 Fault
 350 AtomicSimpleCPU::write(uint32_t data, Addr addr,
 351                        unsigned flags, uint64_t *res);
 352
 353 template
 354 Fault
 355 AtomicSimpleCPU::write(uint16_t data, Addr addr,
 356                        unsigned flags, uint64_t *res);
 357
 358 template
 359 Fault
 360 AtomicSimpleCPU::write(uint8_t data, Addr addr,
 361                        unsigned flags, uint64_t *res);
 362
 363 #endif //DOXYGEN_SHOULD_SKIP_THIS
 364
 365 template<>
 366 Fault
 367 AtomicSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
 368 {
 369     return write(*(uint64_t*)&data, addr, flags, res);
 370 }
 371
 372 template<>
 373 Fault
 374 AtomicSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
 375 {
 376     return write(*(uint32_t*)&data, addr, flags, res);
 377 }
 378
 379
 380 template<>
 381 Fault
 382 AtomicSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 383 {
 384     return write((uint32_t)data, addr, flags, res);
 385 }
 386
 387
 388 void
 389 AtomicSimpleCPU::tick()
 390 {
 391     Tick latency = cycles(1); // instruction takes one cycle by default
 392
 393     for (int i = 0; i < width; ++i) {
 394         numCycles++;
 395
 396         checkForInterrupts();
 397
 398         Fault fault = setupFetchRequest(ifetch_req);
 399
 400         if (fault == NoFault) {
 401             ifetch_pkt->reinitFromRequest();
 402
 403             Tick icache_latency = icachePort.sendAtomic(ifetch_pkt);
 404             // ifetch_req is initialized to read the instruction directly
 405             // into the CPU object's inst field.
 406
 407             dcache_access = false; // assume no dcache access
 408             preExecute();
 409             fault = curStaticInst->execute(this, traceData);
 410             postExecute();
 411
 412             if (simulate_stalls) {
 413                 Tick icache_stall = icache_latency - cycles(1);
 414                 Tick dcache_stall =
 415                     dcache_access ? dcache_latency - cycles(1) : 0;
 416                 Tick stall_cycles = (icache_stall + dcache_stall) / cycles(1);
 417                 if (cycles(stall_cycles) < (icache_stall + dcache_stall))
 418                     latency += cycles(stall_cycles+1);
 419                 else
 420                     latency += cycles(stall_cycles);
 421             }
 422
 423         }
 424
 425         advancePC(fault);
 426     }
 427
 428     if (_status != Idle)
 429         tickEvent.schedule(curTick + latency);
 430 }
 431
 432
 433 ////////////////////////////////////////////////////////////////////////
 434 //
 435 //  AtomicSimpleCPU Simulation Object
 436 //
 437 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
 438
 439     Param<Counter> max_insts_any_thread;
 440     Param<Counter> max_insts_all_threads;
 441     Param<Counter> max_loads_any_thread;
 442     Param<Counter> max_loads_all_threads;
 443     SimObjectParam<MemObject *> mem;
 444
 445 #if FULL_SYSTEM
 446     SimObjectParam<AlphaITB *> itb;
 447     SimObjectParam<AlphaDTB *> dtb;
 448     SimObjectParam<System *> system;
 449     Param<int> cpu_id;
 450     Param<Tick> profile;
 451 #else
 452     SimObjectParam<Process *> workload;
 453 #endif // FULL_SYSTEM
 454
 455     Param<int> clock;
 456
 457     Param<bool> defer_registration;
 458     Param<int> width;
 459     Param<bool> function_trace;
 460     Param<Tick> function_trace_start;
 461     Param<bool> simulate_stalls;
 462
 463 END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
 464
 465 BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
 466
 467     INIT_PARAM(max_insts_any_thread,
 468                "terminate when any thread reaches this inst count"),
 469     INIT_PARAM(max_insts_all_threads,
 470                "terminate when all threads have reached this inst count"),
 471     INIT_PARAM(max_loads_any_thread,
 472                "terminate when any thread reaches this load count"),
 473     INIT_PARAM(max_loads_all_threads,
 474                "terminate when all threads have reached this load count"),
 475     INIT_PARAM(mem, "memory"),
 476
 477 #if FULL_SYSTEM
 478     INIT_PARAM(itb, "Instruction TLB"),
 479     INIT_PARAM(dtb, "Data TLB"),
 480     INIT_PARAM(system, "system object"),
 481     INIT_PARAM(cpu_id, "processor ID"),
 482     INIT_PARAM(profile, ""),
 483 #else
 484     INIT_PARAM(workload, "processes to run"),
 485 #endif // FULL_SYSTEM
 486
 487     INIT_PARAM(clock, "clock speed"),
 488     INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
 489     INIT_PARAM(width, "cpu width"),
 490     INIT_PARAM(function_trace, "Enable function trace"),
 491     INIT_PARAM(function_trace_start, "Cycle to start function trace"),
 492     INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
 493
 494 END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU)
 495
 496
 497 CREATE_SIM_OBJECT(AtomicSimpleCPU)
 498 {
 499     AtomicSimpleCPU::Params *params = new AtomicSimpleCPU::Params();
 500     params->name = getInstanceName();
 501     params->numberOfThreads = 1;
 502     params->max_insts_any_thread = max_insts_any_thread;
 503     params->max_insts_all_threads = max_insts_all_threads;
 504     params->max_loads_any_thread = max_loads_any_thread;
 505     params->max_loads_all_threads = max_loads_all_threads;
 506     params->deferRegistration = defer_registration;
 507     params->clock = clock;
 508     params->functionTrace = function_trace;
 509     params->functionTraceStart = function_trace_start;
 510     params->width = width;
 511     params->simulate_stalls = simulate_stalls;
 512     params->mem = mem;
 513
 514 #if FULL_SYSTEM
 515     params->itb = itb;
 516     params->dtb = dtb;
 517     params->system = system;
 518     params->cpu_id = cpu_id;
 519     params->profile = profile;
 520 #else
 521     params->process = workload;
 522 #endif
 523
 524     AtomicSimpleCPU *cpu = new AtomicSimpleCPU(params);
 525     return cpu;
 526 }
 527
 528 REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU)
 529