2 * Copyright 2014 Google, Inc.
3 * Copyright (c) 2012-2013,2015 ARM Limited
6 * The license below extends only to copyright in the software and shall
7 * not be construed as granting a license to any other intellectual
8 * property including but not limited to intellectual property relating
9 * to a hardware implementation of the functionality of the software
10 * licensed hereunder. You may use the software subject to the license
11 * terms below provided that you ensure that this notice is replicated
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13 * modified or unmodified, in source code or in binary form.
15 * Copyright (c) 2002-2005 The Regents of The University of Michigan
16 * All rights reserved.
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19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
41 * Authors: Steve Reinhardt
44 #include "cpu/simple/atomic.hh"
46 #include "arch/locked_mem.hh"
47 #include "arch/mmapped_ipr.hh"
48 #include "arch/utility.hh"
49 #include "base/bigint.hh"
50 #include "base/output.hh"
51 #include "config/the_isa.hh"
52 #include "cpu/exetrace.hh"
53 #include "debug/Drain.hh"
54 #include "debug/ExecFaulting.hh"
55 #include "debug/SimpleCPU.hh"
56 #include "mem/packet.hh"
57 #include "mem/packet_access.hh"
58 #include "mem/physical.hh"
59 #include "params/AtomicSimpleCPU.hh"
60 #include "sim/faults.hh"
61 #include "sim/full_system.hh"
62 #include "sim/system.hh"
65 using namespace TheISA
;
68 AtomicSimpleCPU::init()
70 BaseSimpleCPU::init();
72 int cid
= threadContexts
[0]->contextId();
73 ifetch_req
.setContext(cid
);
74 data_read_req
.setContext(cid
);
75 data_write_req
.setContext(cid
);
78 AtomicSimpleCPU::AtomicSimpleCPU(AtomicSimpleCPUParams
*p
)
80 tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick",
81 false, Event::CPU_Tick_Pri
),
82 width(p
->width
), locked(false),
83 simulate_data_stalls(p
->simulate_data_stalls
),
84 simulate_inst_stalls(p
->simulate_inst_stalls
),
85 icachePort(name() + ".icache_port", this),
86 dcachePort(name() + ".dcache_port", this),
87 fastmem(p
->fastmem
), dcache_access(false), dcache_latency(0),
94 AtomicSimpleCPU::~AtomicSimpleCPU()
96 if (tickEvent
.scheduled()) {
97 deschedule(tickEvent
);
102 AtomicSimpleCPU::drain()
105 return DrainState::Drained
;
108 DPRINTF(Drain
, "Requesting drain.\n");
109 return DrainState::Draining
;
111 if (tickEvent
.scheduled())
112 deschedule(tickEvent
);
114 activeThreads
.clear();
115 DPRINTF(Drain
, "Not executing microcode, no need to drain.\n");
116 return DrainState::Drained
;
121 AtomicSimpleCPU::threadSnoop(PacketPtr pkt
, ThreadID sender
)
123 DPRINTF(SimpleCPU
, "received snoop pkt for addr:%#x %s\n", pkt
->getAddr(),
126 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
128 if (getCpuAddrMonitor(tid
)->doMonitor(pkt
)) {
132 TheISA::handleLockedSnoop(threadInfo
[tid
]->thread
,
133 pkt
, dcachePort
.cacheBlockMask
);
139 AtomicSimpleCPU::drainResume()
141 assert(!tickEvent
.scheduled());
145 DPRINTF(SimpleCPU
, "Resume\n");
148 assert(!threadContexts
.empty());
150 _status
= BaseSimpleCPU::Idle
;
152 for (ThreadID tid
= 0; tid
< numThreads
; tid
++) {
153 if (threadInfo
[tid
]->thread
->status() == ThreadContext::Active
) {
154 threadInfo
[tid
]->notIdleFraction
= 1;
155 activeThreads
.push_back(tid
);
156 _status
= BaseSimpleCPU::Running
;
158 // Tick if any threads active
159 if (!tickEvent
.scheduled()) {
160 schedule(tickEvent
, nextCycle());
163 threadInfo
[tid
]->notIdleFraction
= 0;
169 AtomicSimpleCPU::tryCompleteDrain()
171 if (drainState() != DrainState::Draining
)
174 DPRINTF(Drain
, "tryCompleteDrain.\n");
178 DPRINTF(Drain
, "CPU done draining, processing drain event\n");
186 AtomicSimpleCPU::switchOut()
188 BaseSimpleCPU::switchOut();
190 assert(!tickEvent
.scheduled());
191 assert(_status
== BaseSimpleCPU::Running
|| _status
== Idle
);
197 AtomicSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
199 BaseSimpleCPU::takeOverFrom(oldCPU
);
201 // The tick event should have been descheduled by drain()
202 assert(!tickEvent
.scheduled());
206 AtomicSimpleCPU::verifyMemoryMode() const
208 if (!system
->isAtomicMode()) {
209 fatal("The atomic CPU requires the memory system to be in "
215 AtomicSimpleCPU::activateContext(ThreadID thread_num
)
217 DPRINTF(SimpleCPU
, "ActivateContext %d\n", thread_num
);
219 assert(thread_num
< numThreads
);
221 threadInfo
[thread_num
]->notIdleFraction
= 1;
222 Cycles delta
= ticksToCycles(threadInfo
[thread_num
]->thread
->lastActivate
-
223 threadInfo
[thread_num
]->thread
->lastSuspend
);
225 ppCycles
->notify(delta
);
227 if (!tickEvent
.scheduled()) {
228 //Make sure ticks are still on multiples of cycles
229 schedule(tickEvent
, clockEdge(Cycles(0)));
231 _status
= BaseSimpleCPU::Running
;
232 if (std::find(activeThreads
.begin(), activeThreads
.end(), thread_num
)
233 == activeThreads
.end()) {
234 activeThreads
.push_back(thread_num
);
237 BaseCPU::activateContext(thread_num
);
242 AtomicSimpleCPU::suspendContext(ThreadID thread_num
)
244 DPRINTF(SimpleCPU
, "SuspendContext %d\n", thread_num
);
246 assert(thread_num
< numThreads
);
247 activeThreads
.remove(thread_num
);
252 assert(_status
== BaseSimpleCPU::Running
);
254 threadInfo
[thread_num
]->notIdleFraction
= 0;
256 if (activeThreads
.empty()) {
259 if (tickEvent
.scheduled()) {
260 deschedule(tickEvent
);
264 BaseCPU::suspendContext(thread_num
);
269 AtomicSimpleCPU::AtomicCPUDPort::recvAtomicSnoop(PacketPtr pkt
)
271 DPRINTF(SimpleCPU
, "received snoop pkt for addr:%#x %s\n", pkt
->getAddr(),
274 // X86 ISA: Snooping an invalidation for monitor/mwait
275 AtomicSimpleCPU
*cpu
= (AtomicSimpleCPU
*)(&owner
);
277 for (ThreadID tid
= 0; tid
< cpu
->numThreads
; tid
++) {
278 if (cpu
->getCpuAddrMonitor(tid
)->doMonitor(pkt
)) {
283 // if snoop invalidates, release any associated locks
284 // When run without caches, Invalidation packets will not be received
285 // hence we must check if the incoming packets are writes and wakeup
286 // the processor accordingly
287 if (pkt
->isInvalidate() || pkt
->isWrite()) {
288 DPRINTF(SimpleCPU
, "received invalidation for addr:%#x\n",
290 for (auto &t_info
: cpu
->threadInfo
) {
291 TheISA::handleLockedSnoop(t_info
->thread
, pkt
, cacheBlockMask
);
299 AtomicSimpleCPU::AtomicCPUDPort::recvFunctionalSnoop(PacketPtr pkt
)
301 DPRINTF(SimpleCPU
, "received snoop pkt for addr:%#x %s\n", pkt
->getAddr(),
304 // X86 ISA: Snooping an invalidation for monitor/mwait
305 AtomicSimpleCPU
*cpu
= (AtomicSimpleCPU
*)(&owner
);
306 for (ThreadID tid
= 0; tid
< cpu
->numThreads
; tid
++) {
307 if (cpu
->getCpuAddrMonitor(tid
)->doMonitor(pkt
)) {
312 // if snoop invalidates, release any associated locks
313 if (pkt
->isInvalidate()) {
314 DPRINTF(SimpleCPU
, "received invalidation for addr:%#x\n",
316 for (auto &t_info
: cpu
->threadInfo
) {
317 TheISA::handleLockedSnoop(t_info
->thread
, pkt
, cacheBlockMask
);
323 AtomicSimpleCPU::readMem(Addr addr
, uint8_t * data
, unsigned size
,
324 Request::Flags flags
)
326 SimpleExecContext
& t_info
= *threadInfo
[curThread
];
327 SimpleThread
* thread
= t_info
.thread
;
329 // use the CPU's statically allocated read request and packet objects
330 Request
*req
= &data_read_req
;
333 traceData
->setMem(addr
, size
, flags
);
335 //The size of the data we're trying to read.
338 //The address of the second part of this access if it needs to be split
339 //across a cache line boundary.
340 Addr secondAddr
= roundDown(addr
+ size
- 1, cacheLineSize());
342 if (secondAddr
> addr
)
343 size
= secondAddr
- addr
;
347 req
->taskId(taskId());
349 req
->setVirt(0, addr
, size
, flags
, dataMasterId(), thread
->pcState().instAddr());
351 // translate to physical address
352 Fault fault
= thread
->dtb
->translateAtomic(req
, thread
->getTC(),
355 // Now do the access.
356 if (fault
== NoFault
&& !req
->getFlags().isSet(Request::NO_ACCESS
)) {
357 Packet
pkt(req
, Packet::makeReadCmd(req
));
358 pkt
.dataStatic(data
);
360 if (req
->isMmappedIpr())
361 dcache_latency
+= TheISA::handleIprRead(thread
->getTC(), &pkt
);
363 if (fastmem
&& system
->isMemAddr(pkt
.getAddr()))
364 system
->getPhysMem().access(&pkt
);
366 dcache_latency
+= dcachePort
.sendAtomic(&pkt
);
368 dcache_access
= true;
370 assert(!pkt
.isError());
373 TheISA::handleLockedRead(thread
, req
);
377 //If there's a fault, return it
378 if (fault
!= NoFault
) {
379 if (req
->isPrefetch()) {
386 //If we don't need to access a second cache line, stop now.
387 if (secondAddr
<= addr
)
389 if (req
->isLockedRMW() && fault
== NoFault
) {
398 * Set up for accessing the second cache line.
401 //Move the pointer we're reading into to the correct location.
403 //Adjust the size to get the remaining bytes.
404 size
= addr
+ fullSize
- secondAddr
;
405 //And access the right address.
411 AtomicSimpleCPU::initiateMemRead(Addr addr
, unsigned size
,
412 Request::Flags flags
)
414 panic("initiateMemRead() is for timing accesses, and should "
415 "never be called on AtomicSimpleCPU.\n");
419 AtomicSimpleCPU::writeMem(uint8_t *data
, unsigned size
, Addr addr
,
420 Request::Flags flags
, uint64_t *res
)
422 SimpleExecContext
& t_info
= *threadInfo
[curThread
];
423 SimpleThread
* thread
= t_info
.thread
;
424 static uint8_t zero_array
[64] = {};
428 assert(flags
& Request::CACHE_BLOCK_ZERO
);
429 // This must be a cache block cleaning request
433 // use the CPU's statically allocated write request and packet objects
434 Request
*req
= &data_write_req
;
437 traceData
->setMem(addr
, size
, flags
);
439 //The size of the data we're trying to read.
442 //The address of the second part of this access if it needs to be split
443 //across a cache line boundary.
444 Addr secondAddr
= roundDown(addr
+ size
- 1, cacheLineSize());
446 if (secondAddr
> addr
)
447 size
= secondAddr
- addr
;
451 req
->taskId(taskId());
453 req
->setVirt(0, addr
, size
, flags
, dataMasterId(), thread
->pcState().instAddr());
455 // translate to physical address
456 Fault fault
= thread
->dtb
->translateAtomic(req
, thread
->getTC(), BaseTLB::Write
);
458 // Now do the access.
459 if (fault
== NoFault
) {
460 MemCmd cmd
= MemCmd::WriteReq
; // default
461 bool do_access
= true; // flag to suppress cache access
464 cmd
= MemCmd::StoreCondReq
;
465 do_access
= TheISA::handleLockedWrite(thread
, req
, dcachePort
.cacheBlockMask
);
466 } else if (req
->isSwap()) {
467 cmd
= MemCmd::SwapReq
;
468 if (req
->isCondSwap()) {
470 req
->setExtraData(*res
);
474 if (do_access
&& !req
->getFlags().isSet(Request::NO_ACCESS
)) {
475 Packet pkt
= Packet(req
, cmd
);
476 pkt
.dataStatic(data
);
478 if (req
->isMmappedIpr()) {
480 TheISA::handleIprWrite(thread
->getTC(), &pkt
);
482 if (fastmem
&& system
->isMemAddr(pkt
.getAddr()))
483 system
->getPhysMem().access(&pkt
);
485 dcache_latency
+= dcachePort
.sendAtomic(&pkt
);
487 // Notify other threads on this CPU of write
488 threadSnoop(&pkt
, curThread
);
490 dcache_access
= true;
491 assert(!pkt
.isError());
495 memcpy(res
, pkt
.getConstPtr
<uint8_t>(), fullSize
);
499 if (res
&& !req
->isSwap()) {
500 *res
= req
->getExtraData();
504 //If there's a fault or we don't need to access a second cache line,
506 if (fault
!= NoFault
|| secondAddr
<= addr
)
508 if (req
->isLockedRMW() && fault
== NoFault
) {
514 if (fault
!= NoFault
&& req
->isPrefetch()) {
522 * Set up for accessing the second cache line.
525 //Move the pointer we're reading into to the correct location.
527 //Adjust the size to get the remaining bytes.
528 size
= addr
+ fullSize
- secondAddr
;
529 //And access the right address.
536 AtomicSimpleCPU::tick()
538 DPRINTF(SimpleCPU
, "Tick\n");
540 // Change thread if multi-threaded
543 // Set memroy request ids to current thread
544 if (numThreads
> 1) {
545 ContextID cid
= threadContexts
[curThread
]->contextId();
547 ifetch_req
.setContext(cid
);
548 data_read_req
.setContext(cid
);
549 data_write_req
.setContext(cid
);
552 SimpleExecContext
& t_info
= *threadInfo
[curThread
];
553 SimpleThread
* thread
= t_info
.thread
;
557 for (int i
= 0; i
< width
|| locked
; ++i
) {
561 if (!curStaticInst
|| !curStaticInst
->isDelayedCommit()) {
562 checkForInterrupts();
566 // We must have just got suspended by a PC event
567 if (_status
== Idle
) {
572 Fault fault
= NoFault
;
574 TheISA::PCState pcState
= thread
->pcState();
576 bool needToFetch
= !isRomMicroPC(pcState
.microPC()) &&
579 ifetch_req
.taskId(taskId());
580 setupFetchRequest(&ifetch_req
);
581 fault
= thread
->itb
->translateAtomic(&ifetch_req
, thread
->getTC(),
585 if (fault
== NoFault
) {
586 Tick icache_latency
= 0;
587 bool icache_access
= false;
588 dcache_access
= false; // assume no dcache access
591 // This is commented out because the decoder would act like
592 // a tiny cache otherwise. It wouldn't be flushed when needed
593 // like the I cache. It should be flushed, and when that works
594 // this code should be uncommented.
595 //Fetch more instruction memory if necessary
596 //if (decoder.needMoreBytes())
598 icache_access
= true;
599 Packet ifetch_pkt
= Packet(&ifetch_req
, MemCmd::ReadReq
);
600 ifetch_pkt
.dataStatic(&inst
);
602 if (fastmem
&& system
->isMemAddr(ifetch_pkt
.getAddr()))
603 system
->getPhysMem().access(&ifetch_pkt
);
605 icache_latency
= icachePort
.sendAtomic(&ifetch_pkt
);
607 assert(!ifetch_pkt
.isError());
609 // ifetch_req is initialized to read the instruction directly
610 // into the CPU object's inst field.
616 Tick stall_ticks
= 0;
618 fault
= curStaticInst
->execute(&t_info
, traceData
);
620 // keep an instruction count
621 if (fault
== NoFault
) {
623 ppCommit
->notify(std::make_pair(thread
, curStaticInst
));
625 else if (traceData
&& !DTRACE(ExecFaulting
)) {
630 if (dynamic_pointer_cast
<SyscallRetryFault
>(fault
)) {
631 // Retry execution of system calls after a delay.
632 // Prevents immediate re-execution since conditions which
633 // caused the retry are unlikely to change every tick.
634 stall_ticks
+= clockEdge(syscallRetryLatency
) - curTick();
640 // @todo remove me after debugging with legion done
641 if (curStaticInst
&& (!curStaticInst
->isMicroop() ||
642 curStaticInst
->isFirstMicroop()))
645 if (simulate_inst_stalls
&& icache_access
)
646 stall_ticks
+= icache_latency
;
648 if (simulate_data_stalls
&& dcache_access
)
649 stall_ticks
+= dcache_latency
;
652 // the atomic cpu does its accounting in ticks, so
653 // keep counting in ticks but round to the clock
655 latency
+= divCeil(stall_ticks
, clockPeriod()) *
660 if (fault
!= NoFault
|| !t_info
.stayAtPC
)
664 if (tryCompleteDrain())
667 // instruction takes at least one cycle
668 if (latency
< clockPeriod())
669 latency
= clockPeriod();
672 reschedule(tickEvent
, curTick() + latency
, true);
676 AtomicSimpleCPU::regProbePoints()
678 BaseCPU::regProbePoints();
680 ppCommit
= new ProbePointArg
<pair
<SimpleThread
*, const StaticInstPtr
>>
681 (getProbeManager(), "Commit");
685 AtomicSimpleCPU::printAddr(Addr a
)
687 dcachePort
.printAddr(a
);
690 ////////////////////////////////////////////////////////////////////////
692 // AtomicSimpleCPU Simulation Object
695 AtomicSimpleCPUParams::create()
697 return new AtomicSimpleCPU(this);