2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/utility.hh"
32 #include "cpu/exetrace.hh"
33 #include "cpu/simple/atomic.hh"
34 #include "mem/packet_impl.hh"
35 #include "sim/builder.hh"
38 using namespace TheISA
;
40 AtomicSimpleCPU::TickEvent::TickEvent(AtomicSimpleCPU
*c
)
41 : Event(&mainEventQueue
, CPU_Tick_Pri
), cpu(c
)
47 AtomicSimpleCPU::TickEvent::process()
53 AtomicSimpleCPU::TickEvent::description()
55 return "AtomicSimpleCPU tick event";
60 AtomicSimpleCPU::init()
62 //Create Memory Ports (conect them up)
63 Port
*mem_dport
= mem
->getPort("");
64 dcachePort
.setPeer(mem_dport
);
65 mem_dport
->setPeer(&dcachePort
);
67 Port
*mem_iport
= mem
->getPort("");
68 icachePort
.setPeer(mem_iport
);
69 mem_iport
->setPeer(&icachePort
);
73 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
74 ThreadContext
*tc
= threadContexts
[i
];
76 // initialize CPU, including PC
77 TheISA::initCPU(tc
, tc
->readCpuId());
83 AtomicSimpleCPU::CpuPort::recvTiming(Packet
*pkt
)
85 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
90 AtomicSimpleCPU::CpuPort::recvAtomic(Packet
*pkt
)
92 panic("AtomicSimpleCPU doesn't expect recvAtomic callback!");
97 AtomicSimpleCPU::CpuPort::recvFunctional(Packet
*pkt
)
99 panic("AtomicSimpleCPU doesn't expect recvFunctional callback!");
103 AtomicSimpleCPU::CpuPort::recvStatusChange(Status status
)
105 if (status
== RangeChange
)
108 panic("AtomicSimpleCPU doesn't expect recvStatusChange callback!");
112 AtomicSimpleCPU::CpuPort::recvRetry()
114 panic("AtomicSimpleCPU doesn't expect recvRetry callback!");
118 AtomicSimpleCPU::AtomicSimpleCPU(Params
*p
)
119 : BaseSimpleCPU(p
), tickEvent(this),
120 width(p
->width
), simulate_stalls(p
->simulate_stalls
),
121 icachePort(name() + "-iport", this), dcachePort(name() + "-iport", this)
125 // @todo fix me and get the real cpu id & thread number!!!
126 ifetch_req
= new Request();
127 ifetch_req
->setThreadContext(0,0); //Need CPU/Thread IDS HERE
128 ifetch_pkt
= new Packet(ifetch_req
, Packet::ReadReq
, Packet::Broadcast
);
129 ifetch_pkt
->dataStatic(&inst
);
131 data_read_req
= new Request();
132 data_read_req
->setThreadContext(0,0); //Need CPU/Thread IDS HERE
133 data_read_pkt
= new Packet(data_read_req
, Packet::ReadReq
,
135 data_read_pkt
->dataStatic(&dataReg
);
137 data_write_req
= new Request();
138 data_write_req
->setThreadContext(0,0); //Need CPU/Thread IDS HERE
139 data_write_pkt
= new Packet(data_write_req
, Packet::WriteReq
,
144 AtomicSimpleCPU::~AtomicSimpleCPU()
149 AtomicSimpleCPU::serialize(ostream
&os
)
151 SERIALIZE_ENUM(_status
);
152 BaseSimpleCPU::serialize(os
);
153 nameOut(os
, csprintf("%s.tickEvent", name()));
154 tickEvent
.serialize(os
);
158 AtomicSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
160 UNSERIALIZE_ENUM(_status
);
161 BaseSimpleCPU::unserialize(cp
, section
);
162 tickEvent
.unserialize(cp
, csprintf("%s.tickEvent", section
));
166 AtomicSimpleCPU::switchOut()
168 assert(status() == Running
|| status() == Idle
);
169 _status
= SwitchedOut
;
176 AtomicSimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
178 BaseCPU::takeOverFrom(oldCPU
);
180 assert(!tickEvent
.scheduled());
182 // if any of this CPU's ThreadContexts are active, mark the CPU as
183 // running and schedule its tick event.
184 for (int i
= 0; i
< threadContexts
.size(); ++i
) {
185 ThreadContext
*tc
= threadContexts
[i
];
186 if (tc
->status() == ThreadContext::Active
&& _status
!= Running
) {
188 tickEvent
.schedule(curTick
);
196 AtomicSimpleCPU::activateContext(int thread_num
, int delay
)
198 assert(thread_num
== 0);
201 assert(_status
== Idle
);
202 assert(!tickEvent
.scheduled());
205 tickEvent
.schedule(curTick
+ cycles(delay
));
211 AtomicSimpleCPU::suspendContext(int thread_num
)
213 assert(thread_num
== 0);
216 assert(_status
== Running
);
218 // tick event may not be scheduled if this gets called from inside
219 // an instruction's execution, e.g. "quiesce"
220 if (tickEvent
.scheduled())
221 tickEvent
.deschedule();
230 AtomicSimpleCPU::read(Addr addr
, T
&data
, unsigned flags
)
232 data_read_req
->setVirt(0, addr
, sizeof(T
), flags
, thread
->readPC());
235 traceData
->setAddr(addr
);
238 // translate to physical address
239 Fault fault
= thread
->translateDataReadReq(data_read_req
);
241 // Now do the access.
242 if (fault
== NoFault
) {
243 data_read_pkt
->reinitFromRequest();
245 dcache_latency
= dcachePort
.sendAtomic(data_read_pkt
);
246 dcache_access
= true;
248 assert(data_read_pkt
->result
== Packet::Success
);
249 data
= data_read_pkt
->get
<T
>();
253 // This will need a new way to tell if it has a dcache attached.
254 if (data_read_req
->getFlags() & UNCACHEABLE
)
255 recordEvent("Uncached Read");
260 #ifndef DOXYGEN_SHOULD_SKIP_THIS
264 AtomicSimpleCPU::read(Addr addr
, uint64_t &data
, unsigned flags
);
268 AtomicSimpleCPU::read(Addr addr
, uint32_t &data
, unsigned flags
);
272 AtomicSimpleCPU::read(Addr addr
, uint16_t &data
, unsigned flags
);
276 AtomicSimpleCPU::read(Addr addr
, uint8_t &data
, unsigned flags
);
278 #endif //DOXYGEN_SHOULD_SKIP_THIS
282 AtomicSimpleCPU::read(Addr addr
, double &data
, unsigned flags
)
284 return read(addr
, *(uint64_t*)&data
, flags
);
289 AtomicSimpleCPU::read(Addr addr
, float &data
, unsigned flags
)
291 return read(addr
, *(uint32_t*)&data
, flags
);
297 AtomicSimpleCPU::read(Addr addr
, int32_t &data
, unsigned flags
)
299 return read(addr
, (uint32_t&)data
, flags
);
305 AtomicSimpleCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
307 data_write_req
->setVirt(0, addr
, sizeof(T
), flags
, thread
->readPC());
310 traceData
->setAddr(addr
);
313 // translate to physical address
314 Fault fault
= thread
->translateDataWriteReq(data_write_req
);
316 // Now do the access.
317 if (fault
== NoFault
) {
319 data_write_pkt
->reinitFromRequest();
320 data_write_pkt
->dataStatic(&data
);
322 dcache_latency
= dcachePort
.sendAtomic(data_write_pkt
);
323 dcache_access
= true;
325 assert(data_write_pkt
->result
== Packet::Success
);
327 if (res
&& data_write_req
->getFlags() & LOCKED
) {
328 *res
= data_write_req
->getScResult();
332 // This will need a new way to tell if it's hooked up to a cache or not.
333 if (data_write_req
->getFlags() & UNCACHEABLE
)
334 recordEvent("Uncached Write");
336 // If the write needs to have a fault on the access, consider calling
337 // changeStatus() and changing it to "bad addr write" or something.
342 #ifndef DOXYGEN_SHOULD_SKIP_THIS
345 AtomicSimpleCPU::write(uint64_t data
, Addr addr
,
346 unsigned flags
, uint64_t *res
);
350 AtomicSimpleCPU::write(uint32_t data
, Addr addr
,
351 unsigned flags
, uint64_t *res
);
355 AtomicSimpleCPU::write(uint16_t data
, Addr addr
,
356 unsigned flags
, uint64_t *res
);
360 AtomicSimpleCPU::write(uint8_t data
, Addr addr
,
361 unsigned flags
, uint64_t *res
);
363 #endif //DOXYGEN_SHOULD_SKIP_THIS
367 AtomicSimpleCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
369 return write(*(uint64_t*)&data
, addr
, flags
, res
);
374 AtomicSimpleCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
376 return write(*(uint32_t*)&data
, addr
, flags
, res
);
382 AtomicSimpleCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
384 return write((uint32_t)data
, addr
, flags
, res
);
389 AtomicSimpleCPU::tick()
391 Tick latency
= cycles(1); // instruction takes one cycle by default
393 for (int i
= 0; i
< width
; ++i
) {
396 checkForInterrupts();
398 Fault fault
= setupFetchRequest(ifetch_req
);
400 if (fault
== NoFault
) {
401 ifetch_pkt
->reinitFromRequest();
403 Tick icache_latency
= icachePort
.sendAtomic(ifetch_pkt
);
404 // ifetch_req is initialized to read the instruction directly
405 // into the CPU object's inst field.
407 dcache_access
= false; // assume no dcache access
409 fault
= curStaticInst
->execute(this, traceData
);
412 if (simulate_stalls
) {
413 Tick icache_stall
= icache_latency
- cycles(1);
415 dcache_access
? dcache_latency
- cycles(1) : 0;
416 Tick stall_cycles
= (icache_stall
+ dcache_stall
) / cycles(1);
417 if (cycles(stall_cycles
) < (icache_stall
+ dcache_stall
))
418 latency
+= cycles(stall_cycles
+1);
420 latency
+= cycles(stall_cycles
);
429 tickEvent
.schedule(curTick
+ latency
);
433 ////////////////////////////////////////////////////////////////////////
435 // AtomicSimpleCPU Simulation Object
437 BEGIN_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU
)
439 Param
<Counter
> max_insts_any_thread
;
440 Param
<Counter
> max_insts_all_threads
;
441 Param
<Counter
> max_loads_any_thread
;
442 Param
<Counter
> max_loads_all_threads
;
443 SimObjectParam
<MemObject
*> mem
;
446 SimObjectParam
<AlphaITB
*> itb
;
447 SimObjectParam
<AlphaDTB
*> dtb
;
448 SimObjectParam
<System
*> system
;
452 SimObjectParam
<Process
*> workload
;
453 #endif // FULL_SYSTEM
457 Param
<bool> defer_registration
;
459 Param
<bool> function_trace
;
460 Param
<Tick
> function_trace_start
;
461 Param
<bool> simulate_stalls
;
463 END_DECLARE_SIM_OBJECT_PARAMS(AtomicSimpleCPU
)
465 BEGIN_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU
)
467 INIT_PARAM(max_insts_any_thread
,
468 "terminate when any thread reaches this inst count"),
469 INIT_PARAM(max_insts_all_threads
,
470 "terminate when all threads have reached this inst count"),
471 INIT_PARAM(max_loads_any_thread
,
472 "terminate when any thread reaches this load count"),
473 INIT_PARAM(max_loads_all_threads
,
474 "terminate when all threads have reached this load count"),
475 INIT_PARAM(mem
, "memory"),
478 INIT_PARAM(itb
, "Instruction TLB"),
479 INIT_PARAM(dtb
, "Data TLB"),
480 INIT_PARAM(system
, "system object"),
481 INIT_PARAM(cpu_id
, "processor ID"),
482 INIT_PARAM(profile
, ""),
484 INIT_PARAM(workload
, "processes to run"),
485 #endif // FULL_SYSTEM
487 INIT_PARAM(clock
, "clock speed"),
488 INIT_PARAM(defer_registration
, "defer system registration (for sampling)"),
489 INIT_PARAM(width
, "cpu width"),
490 INIT_PARAM(function_trace
, "Enable function trace"),
491 INIT_PARAM(function_trace_start
, "Cycle to start function trace"),
492 INIT_PARAM(simulate_stalls
, "Simulate cache stall cycles")
494 END_INIT_SIM_OBJECT_PARAMS(AtomicSimpleCPU
)
497 CREATE_SIM_OBJECT(AtomicSimpleCPU
)
499 AtomicSimpleCPU::Params
*params
= new AtomicSimpleCPU::Params();
500 params
->name
= getInstanceName();
501 params
->numberOfThreads
= 1;
502 params
->max_insts_any_thread
= max_insts_any_thread
;
503 params
->max_insts_all_threads
= max_insts_all_threads
;
504 params
->max_loads_any_thread
= max_loads_any_thread
;
505 params
->max_loads_all_threads
= max_loads_all_threads
;
506 params
->deferRegistration
= defer_registration
;
507 params
->clock
= clock
;
508 params
->functionTrace
= function_trace
;
509 params
->functionTraceStart
= function_trace_start
;
510 params
->width
= width
;
511 params
->simulate_stalls
= simulate_stalls
;
517 params
->system
= system
;
518 params
->cpu_id
= cpu_id
;
519 params
->profile
= profile
;
521 params
->process
= workload
;
524 AtomicSimpleCPU
*cpu
= new AtomicSimpleCPU(params
);
528 REGISTER_SIM_OBJECT("AtomicSimpleCPU", AtomicSimpleCPU
)