2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #ifndef __CPU_SIMPLE_ATOMIC_HH__
32 #define __CPU_SIMPLE_ATOMIC_HH__
34 #include "cpu/simple/base.hh"
35 #include "params/AtomicSimpleCPU.hh"
37 class AtomicSimpleCPU : public BaseSimpleCPU
41 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
42 virtual ~AtomicSimpleCPU();
48 struct TickEvent : public Event
52 TickEvent(AtomicSimpleCPU *c);
54 const char *description() const;
60 const bool simulate_data_stalls;
61 const bool simulate_inst_stalls;
63 // main simulation loop (one cycle)
66 class CpuPort : public Port
70 CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
71 : Port(_name, _cpu), cpu(_cpu)
80 virtual bool recvTiming(PacketPtr pkt);
82 virtual Tick recvAtomic(PacketPtr pkt);
84 virtual void recvFunctional(PacketPtr pkt);
86 virtual void recvStatusChange(Status status);
88 virtual void recvRetry();
90 virtual void getDeviceAddressRanges(AddrRangeList &resp,
92 { resp.clear(); snoop = true; }
97 class DcachePort : public CpuPort
100 DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu)
101 : CpuPort(_name, _cpu)
104 virtual void setPeer(Port *port);
106 DcachePort dcachePort;
111 Request data_read_req;
112 Request data_write_req;
117 Range<Addr> physMemAddr;
121 virtual Port *getPort(const std::string &if_name, int idx = -1);
123 virtual void serialize(std::ostream &os);
124 virtual void unserialize(Checkpoint *cp, const std::string §ion);
125 virtual void resume();
128 void takeOverFrom(BaseCPU *oldCPU);
130 virtual void activateContext(int thread_num, int delay);
131 virtual void suspendContext(int thread_num);
134 Fault read(Addr addr, T &data, unsigned flags);
137 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
139 Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
140 int size, unsigned flags);
141 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
142 int size, unsigned flags);
145 * Print state of address in memory system via PrintReq (for
148 void printAddr(Addr a);
151 #endif // __CPU_SIMPLE_ATOMIC_HH__