src/cpu/simple/atomic.hh

   1 /*
   2  * Copyright (c) 2012-2013 ARM Limited
   3  * All rights reserved.
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Steve Reinhardt
  41  */
  42
  43 #ifndef __CPU_SIMPLE_ATOMIC_HH__
  44 #define __CPU_SIMPLE_ATOMIC_HH__
  45
  46 #include "base/hashmap.hh"
  47 #include "cpu/simple/base.hh"
  48 #include "params/AtomicSimpleCPU.hh"
  49
  50 /**
  51  *  Start and end address of basic block for SimPoint profiling.
  52  *  This structure is used to look up the hash table of BBVs.
  53  *  - first: PC of first inst in basic block
  54  *  - second: PC of last inst in basic block
  55  */
  56 typedef std::pair<Addr, Addr> BasicBlockRange;
  57
  58 /** Overload hash function for BasicBlockRange type */
  59 __hash_namespace_begin
  60 template <>
  61 struct hash<BasicBlockRange>
  62 {
  63   public:
  64     size_t operator()(const BasicBlockRange &bb) const {
  65         return hash<Addr>()(bb.first + bb.second);
  66     }
  67 };
  68 __hash_namespace_end
  69
  70
  71 class AtomicSimpleCPU : public BaseSimpleCPU
  72 {
  73   public:
  74
  75     AtomicSimpleCPU(AtomicSimpleCPUParams *params);
  76     virtual ~AtomicSimpleCPU();
  77
  78     virtual void init();
  79
  80   private:
  81
  82     struct TickEvent : public Event
  83     {
  84         AtomicSimpleCPU *cpu;
  85
  86         TickEvent(AtomicSimpleCPU *c);
  87         void process();
  88         const char *description() const;
  89     };
  90
  91     TickEvent tickEvent;
  92
  93     const int width;
  94     bool locked;
  95     const bool simulate_data_stalls;
  96     const bool simulate_inst_stalls;
  97
  98     /**
  99      * Drain manager to use when signaling drain completion
 100      *
 101      * This pointer is non-NULL when draining and NULL otherwise.
 102      */
 103     DrainManager *drain_manager;
 104
 105     // main simulation loop (one cycle)
 106     void tick();
 107
 108     /**
 109      * Check if a system is in a drained state.
 110      *
 111      * We need to drain if:
 112      * <ul>
 113      * <li>We are in the middle of a microcode sequence as some CPUs
 114      *     (e.g., HW accelerated CPUs) can't be started in the middle
 115      *     of a gem5 microcode sequence.
 116      *
 117      * <li>The CPU is in a LLSC region. This shouldn't normally happen
 118      *     as these are executed atomically within a single tick()
 119      *     call. The only way this can happen at the moment is if
 120      *     there is an event in the PC event queue that affects the
 121      *     CPU state while it is in an LLSC region.
 122      *
 123      * <li>Stay at PC is true.
 124      * </ul>
 125      */
 126     bool isDrained() {
 127         return microPC() == 0 &&
 128             !locked &&
 129             !stayAtPC;
 130     }
 131
 132     /**
 133      * Try to complete a drain request.
 134      *
 135      * @returns true if the CPU is drained, false otherwise.
 136      */
 137     bool tryCompleteDrain();
 138
 139     /**
 140      * An AtomicCPUPort overrides the default behaviour of the
 141      * recvAtomicSnoop and ignores the packet instead of panicking. It
 142      * also provides an implementation for the purely virtual timing
 143      * functions and panics on either of these.
 144      */
 145     class AtomicCPUPort : public MasterPort
 146     {
 147
 148       public:
 149
 150         AtomicCPUPort(const std::string &_name, BaseCPU* _cpu)
 151             : MasterPort(_name, _cpu)
 152         { }
 153
 154       protected:
 155
 156         virtual Tick recvAtomicSnoop(PacketPtr pkt)
 157         {
 158             // Snooping a coherence request, just return
 159             return 0;
 160         }
 161
 162         bool recvTimingResp(PacketPtr pkt)
 163         {
 164             panic("Atomic CPU doesn't expect recvTimingResp!\n");
 165             return true;
 166         }
 167
 168         void recvRetry()
 169         {
 170             panic("Atomic CPU doesn't expect recvRetry!\n");
 171         }
 172
 173     };
 174
 175     AtomicCPUPort icachePort;
 176     AtomicCPUPort dcachePort;
 177
 178     bool fastmem;
 179     Request ifetch_req;
 180     Request data_read_req;
 181     Request data_write_req;
 182
 183     bool dcache_access;
 184     Tick dcache_latency;
 185
 186     /**
 187      * Profile basic blocks for SimPoints.
 188      * Called at every macro inst to increment basic block inst counts and
 189      * to profile block if end of block.
 190      */
 191     void profileSimPoint();
 192
 193     /** Data structures for SimPoints BBV generation
 194      *  @{
 195      */
 196
 197     /** Whether SimPoint BBV profiling is enabled */
 198     const bool simpoint;
 199     /** SimPoint profiling interval size in instructions */
 200     const uint64_t intervalSize;
 201
 202     /** Inst count in current basic block */
 203     uint64_t intervalCount;
 204     /** Excess inst count from previous interval*/
 205     uint64_t intervalDrift;
 206     /** Pointer to SimPoint BBV output stream */
 207     std::ostream *simpointStream;
 208
 209     /** Basic Block information */
 210     struct BBInfo {
 211         /** Unique ID */
 212         uint64_t id;
 213         /** Num of static insts in BB */
 214         uint64_t insts;
 215         /** Accumulated dynamic inst count executed by BB */
 216         uint64_t count;
 217     };
 218
 219     /** Hash table containing all previously seen basic blocks */
 220     m5::hash_map<BasicBlockRange, BBInfo> bbMap;
 221     /** Currently executing basic block */
 222     BasicBlockRange currentBBV;
 223     /** inst count in current basic block */
 224     uint64_t currentBBVInstCount;
 225
 226     /** @}
 227      *  End of data structures for SimPoints BBV generation
 228      */
 229
 230   protected:
 231
 232     /** Return a reference to the data port. */
 233     virtual MasterPort &getDataPort() { return dcachePort; }
 234
 235     /** Return a reference to the instruction port. */
 236     virtual MasterPort &getInstPort() { return icachePort; }
 237
 238   public:
 239
 240     unsigned int drain(DrainManager *drain_manager);
 241     void drainResume();
 242
 243     void switchOut();
 244     void takeOverFrom(BaseCPU *oldCPU);
 245
 246     void verifyMemoryMode() const;
 247
 248     virtual void activateContext(ThreadID thread_num, Cycles delay);
 249     virtual void suspendContext(ThreadID thread_num);
 250
 251     Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
 252
 253     Fault writeMem(uint8_t *data, unsigned size,
 254                    Addr addr, unsigned flags, uint64_t *res);
 255
 256     /**
 257      * Print state of address in memory system via PrintReq (for
 258      * debugging).
 259      */
 260     void printAddr(Addr a);
 261 };
 262
 263 #endif // __CPU_SIMPLE_ATOMIC_HH__