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14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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40 * Authors: Steve Reinhardt
43 #ifndef __CPU_SIMPLE_ATOMIC_HH__
44 #define __CPU_SIMPLE_ATOMIC_HH__
46 #include "cpu/simple/base.hh"
47 #include "cpu/simple/exec_context.hh"
48 #include "mem/request.hh"
49 #include "params/AtomicSimpleCPU.hh"
50 #include "sim/probe/probe.hh"
52 class AtomicSimpleCPU : public BaseSimpleCPU
56 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
57 virtual ~AtomicSimpleCPU();
63 EventFunctionWrapper tickEvent;
67 const bool simulate_data_stalls;
68 const bool simulate_inst_stalls;
70 // main simulation loop (one cycle)
74 * Check if a system is in a drained state.
76 * We need to drain if:
78 * <li>We are in the middle of a microcode sequence as some CPUs
79 * (e.g., HW accelerated CPUs) can't be started in the middle
80 * of a gem5 microcode sequence.
82 * <li>The CPU is in a LLSC region. This shouldn't normally happen
83 * as these are executed atomically within a single tick()
84 * call. The only way this can happen at the moment is if
85 * there is an event in the PC event queue that affects the
86 * CPU state while it is in an LLSC region.
88 * <li>Stay at PC is true.
92 SimpleExecContext &t_info = *threadInfo[curThread];
94 return t_info.thread->microPC() == 0 &&
100 * Try to complete a drain request.
102 * @returns true if the CPU is drained, false otherwise.
104 bool tryCompleteDrain();
107 * An AtomicCPUPort overrides the default behaviour of the
108 * recvAtomicSnoop and ignores the packet instead of panicking. It
109 * also provides an implementation for the purely virtual timing
110 * functions and panics on either of these.
112 class AtomicCPUPort : public MasterPort
117 AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
118 : MasterPort(_name, _cpu)
123 bool recvTimingResp(PacketPtr pkt)
125 panic("Atomic CPU doesn't expect recvTimingResp!\n");
131 panic("Atomic CPU doesn't expect recvRetry!\n");
136 class AtomicCPUDPort : public AtomicCPUPort
141 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu)
142 : AtomicCPUPort(_name, _cpu), cpu(_cpu)
144 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
147 bool isSnooping() const { return true; }
153 virtual Tick recvAtomicSnoop(PacketPtr pkt);
154 virtual void recvFunctionalSnoop(PacketPtr pkt);
158 AtomicCPUPort icachePort;
159 AtomicCPUDPort dcachePort;
163 Request data_read_req;
164 Request data_write_req;
170 ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit;
174 /** Return a reference to the data port. */
175 MasterPort &getDataPort() override { return dcachePort; }
177 /** Return a reference to the instruction port. */
178 MasterPort &getInstPort() override { return icachePort; }
180 /** Perform snoop for other cpu-local thread contexts. */
181 void threadSnoop(PacketPtr pkt, ThreadID sender);
185 DrainState drain() override;
186 void drainResume() override;
188 void switchOut() override;
189 void takeOverFrom(BaseCPU *oldCPU) override;
191 void verifyMemoryMode() const override;
193 void activateContext(ThreadID thread_num) override;
194 void suspendContext(ThreadID thread_num) override;
196 Fault readMem(Addr addr, uint8_t *data, unsigned size,
197 Request::Flags flags) override;
199 Fault initiateMemRead(Addr addr, unsigned size,
200 Request::Flags flags) override;
202 Fault writeMem(uint8_t *data, unsigned size,
203 Addr addr, Request::Flags flags, uint64_t *res) override;
205 void regProbePoints() override;
208 * Print state of address in memory system via PrintReq (for
211 void printAddr(Addr a);
214 #endif // __CPU_SIMPLE_ATOMIC_HH__