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40 * Authors: Steve Reinhardt
43 #ifndef __CPU_SIMPLE_ATOMIC_HH__
44 #define __CPU_SIMPLE_ATOMIC_HH__
46 #include "cpu/simple/base.hh"
47 #include "params/AtomicSimpleCPU.hh"
49 class AtomicSimpleCPU : public BaseSimpleCPU
53 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
54 virtual ~AtomicSimpleCPU();
60 struct TickEvent : public Event
64 TickEvent(AtomicSimpleCPU *c);
66 const char *description() const;
73 const bool simulate_data_stalls;
74 const bool simulate_inst_stalls;
77 * Drain manager to use when signaling drain completion
79 * This pointer is non-NULL when draining and NULL otherwise.
81 DrainManager *drain_manager;
83 // main simulation loop (one cycle)
87 * Check if a system is in a drained state.
89 * We need to drain if:
91 * <li>We are in the middle of a microcode sequence as some CPUs
92 * (e.g., HW accelerated CPUs) can't be started in the middle
93 * of a gem5 microcode sequence.
95 * <li>The CPU is in a LLSC region. This shouldn't normally happen
96 * as these are executed atomically within a single tick()
97 * call. The only way this can happen at the moment is if
98 * there is an event in the PC event queue that affects the
99 * CPU state while it is in an LLSC region.
101 * <li>Stay at PC is true.
105 return microPC() == 0 &&
111 * Try to complete a drain request.
113 * @returns true if the CPU is drained, false otherwise.
115 bool tryCompleteDrain();
118 * An AtomicCPUPort overrides the default behaviour of the
119 * recvAtomicSnoop and ignores the packet instead of panicking. It
120 * also provides an implementation for the purely virtual timing
121 * functions and panics on either of these.
123 class AtomicCPUPort : public MasterPort
128 AtomicCPUPort(const std::string &_name, BaseCPU* _cpu)
129 : MasterPort(_name, _cpu)
134 virtual Tick recvAtomicSnoop(PacketPtr pkt)
136 // Snooping a coherence request, just return
140 bool recvTimingResp(PacketPtr pkt)
142 panic("Atomic CPU doesn't expect recvTimingResp!\n");
148 panic("Atomic CPU doesn't expect recvRetry!\n");
153 AtomicCPUPort icachePort;
154 AtomicCPUPort dcachePort;
158 Request data_read_req;
159 Request data_write_req;
166 /** Return a reference to the data port. */
167 virtual MasterPort &getDataPort() { return dcachePort; }
169 /** Return a reference to the instruction port. */
170 virtual MasterPort &getInstPort() { return icachePort; }
174 unsigned int drain(DrainManager *drain_manager);
178 void takeOverFrom(BaseCPU *oldCPU);
180 void verifyMemoryMode() const;
182 virtual void activateContext(ThreadID thread_num, Cycles delay);
183 virtual void suspendContext(ThreadID thread_num);
185 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
187 Fault writeMem(uint8_t *data, unsigned size,
188 Addr addr, unsigned flags, uint64_t *res);
191 * Print state of address in memory system via PrintReq (for
194 void printAddr(Addr a);
197 #endif // __CPU_SIMPLE_ATOMIC_HH__