2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #ifndef __CPU_SIMPLE_ATOMIC_HH__
32 #define __CPU_SIMPLE_ATOMIC_HH__
34 #include "cpu/simple/base.hh"
36 class AtomicSimpleCPU : public BaseSimpleCPU
40 struct Params : public BaseSimpleCPU::Params {
42 bool simulate_data_stalls;
43 bool simulate_inst_stalls;
46 AtomicSimpleCPU(Params *params);
47 virtual ~AtomicSimpleCPU();
62 Status status() const { return _status; }
66 struct TickEvent : public Event
70 TickEvent(AtomicSimpleCPU *c);
72 const char *description() const;
78 const bool simulate_data_stalls;
79 const bool simulate_inst_stalls;
81 // main simulation loop (one cycle)
84 class CpuPort : public Port
88 CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
89 : Port(_name, _cpu), cpu(_cpu)
98 virtual bool recvTiming(PacketPtr pkt);
100 virtual Tick recvAtomic(PacketPtr pkt);
102 virtual void recvFunctional(PacketPtr pkt);
104 virtual void recvStatusChange(Status status);
106 virtual void recvRetry();
108 virtual void getDeviceAddressRanges(AddrRangeList &resp,
110 { resp.clear(); snoop = true; }
115 class DcachePort : public CpuPort
118 DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu)
119 : CpuPort(_name, _cpu)
122 virtual void setPeer(Port *port);
124 DcachePort dcachePort;
129 Request data_read_req;
130 Request data_write_req;
135 Range<Addr> physMemAddr;
139 virtual Port *getPort(const std::string &if_name, int idx = -1);
141 virtual void serialize(std::ostream &os);
142 virtual void unserialize(Checkpoint *cp, const std::string §ion);
143 virtual void resume();
146 void takeOverFrom(BaseCPU *oldCPU);
148 virtual void activateContext(int thread_num, int delay);
149 virtual void suspendContext(int thread_num);
152 Fault read(Addr addr, T &data, unsigned flags);
155 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
157 Fault translateDataReadAddr(Addr vaddr, Addr &paddr,
158 int size, unsigned flags);
159 Fault translateDataWriteAddr(Addr vaddr, Addr &paddr,
160 int size, unsigned flags);
163 * Print state of address in memory system via PrintReq (for
166 void printAddr(Addr a);
169 #endif // __CPU_SIMPLE_ATOMIC_HH__