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40 * Authors: Steve Reinhardt
43 #ifndef __CPU_SIMPLE_ATOMIC_HH__
44 #define __CPU_SIMPLE_ATOMIC_HH__
46 #include "cpu/simple/base.hh"
47 #include "cpu/simple/exec_context.hh"
48 #include "mem/request.hh"
49 #include "params/AtomicSimpleCPU.hh"
50 #include "sim/probe/probe.hh"
52 class AtomicSimpleCPU : public BaseSimpleCPU
56 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
57 virtual ~AtomicSimpleCPU();
63 struct TickEvent : public Event
67 TickEvent(AtomicSimpleCPU *c);
69 const char *description() const;
76 const bool simulate_data_stalls;
77 const bool simulate_inst_stalls;
79 // main simulation loop (one cycle)
83 * Check if a system is in a drained state.
85 * We need to drain if:
87 * <li>We are in the middle of a microcode sequence as some CPUs
88 * (e.g., HW accelerated CPUs) can't be started in the middle
89 * of a gem5 microcode sequence.
91 * <li>The CPU is in a LLSC region. This shouldn't normally happen
92 * as these are executed atomically within a single tick()
93 * call. The only way this can happen at the moment is if
94 * there is an event in the PC event queue that affects the
95 * CPU state while it is in an LLSC region.
97 * <li>Stay at PC is true.
101 SimpleExecContext &t_info = *threadInfo[curThread];
103 return t_info.thread->microPC() == 0 &&
109 * Try to complete a drain request.
111 * @returns true if the CPU is drained, false otherwise.
113 bool tryCompleteDrain();
116 * An AtomicCPUPort overrides the default behaviour of the
117 * recvAtomicSnoop and ignores the packet instead of panicking. It
118 * also provides an implementation for the purely virtual timing
119 * functions and panics on either of these.
121 class AtomicCPUPort : public MasterPort
126 AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
127 : MasterPort(_name, _cpu)
132 bool recvTimingResp(PacketPtr pkt)
134 panic("Atomic CPU doesn't expect recvTimingResp!\n");
140 panic("Atomic CPU doesn't expect recvRetry!\n");
145 class AtomicCPUDPort : public AtomicCPUPort
150 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu)
151 : AtomicCPUPort(_name, _cpu), cpu(_cpu)
153 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
156 bool isSnooping() const { return true; }
162 virtual Tick recvAtomicSnoop(PacketPtr pkt);
163 virtual void recvFunctionalSnoop(PacketPtr pkt);
167 AtomicCPUPort icachePort;
168 AtomicCPUDPort dcachePort;
172 Request data_read_req;
173 Request data_write_req;
179 ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit;
183 /** Return a reference to the data port. */
184 MasterPort &getDataPort() override { return dcachePort; }
186 /** Return a reference to the instruction port. */
187 MasterPort &getInstPort() override { return icachePort; }
189 /** Perform snoop for other cpu-local thread contexts. */
190 void threadSnoop(PacketPtr pkt, ThreadID sender);
194 DrainState drain() override;
195 void drainResume() override;
197 void switchOut() override;
198 void takeOverFrom(BaseCPU *oldCPU) override;
200 void verifyMemoryMode() const override;
202 void activateContext(ThreadID thread_num) override;
203 void suspendContext(ThreadID thread_num) override;
205 Fault readMem(Addr addr, uint8_t *data, unsigned size,
206 Request::Flags flags) override;
208 Fault initiateMemRead(Addr addr, unsigned size,
209 Request::Flags flags) override;
211 Fault writeMem(uint8_t *data, unsigned size,
212 Addr addr, Request::Flags flags, uint64_t *res) override;
214 void regProbePoints() override;
217 * Print state of address in memory system via PrintReq (for
220 void printAddr(Addr a);
223 #endif // __CPU_SIMPLE_ATOMIC_HH__