2 * Copyright (c) 2012-2013 ARM Limited
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14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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26 * this software without specific prior written permission.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 * Authors: Steve Reinhardt
43 #ifndef __CPU_SIMPLE_ATOMIC_HH__
44 #define __CPU_SIMPLE_ATOMIC_HH__
46 #include "base/hashmap.hh"
47 #include "cpu/simple/base.hh"
48 #include "params/AtomicSimpleCPU.hh"
51 * Start and end address of basic block for SimPoint profiling.
52 * This structure is used to look up the hash table of BBVs.
53 * - first: PC of first inst in basic block
54 * - second: PC of last inst in basic block
56 typedef std::pair<Addr, Addr> BasicBlockRange;
58 /** Overload hash function for BasicBlockRange type */
59 __hash_namespace_begin
61 struct hash<BasicBlockRange>
64 size_t operator()(const BasicBlockRange &bb) const {
65 return hash<Addr>()(bb.first + bb.second);
71 class AtomicSimpleCPU : public BaseSimpleCPU
75 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
76 virtual ~AtomicSimpleCPU();
82 struct TickEvent : public Event
86 TickEvent(AtomicSimpleCPU *c);
88 const char *description() const;
95 const bool simulate_data_stalls;
96 const bool simulate_inst_stalls;
99 * Drain manager to use when signaling drain completion
101 * This pointer is non-NULL when draining and NULL otherwise.
103 DrainManager *drain_manager;
105 // main simulation loop (one cycle)
109 * Check if a system is in a drained state.
111 * We need to drain if:
113 * <li>We are in the middle of a microcode sequence as some CPUs
114 * (e.g., HW accelerated CPUs) can't be started in the middle
115 * of a gem5 microcode sequence.
117 * <li>The CPU is in a LLSC region. This shouldn't normally happen
118 * as these are executed atomically within a single tick()
119 * call. The only way this can happen at the moment is if
120 * there is an event in the PC event queue that affects the
121 * CPU state while it is in an LLSC region.
123 * <li>Stay at PC is true.
127 return microPC() == 0 &&
133 * Try to complete a drain request.
135 * @returns true if the CPU is drained, false otherwise.
137 bool tryCompleteDrain();
140 * An AtomicCPUPort overrides the default behaviour of the
141 * recvAtomicSnoop and ignores the packet instead of panicking. It
142 * also provides an implementation for the purely virtual timing
143 * functions and panics on either of these.
145 class AtomicCPUPort : public MasterPort
150 AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
151 : MasterPort(_name, _cpu)
155 virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
157 bool recvTimingResp(PacketPtr pkt)
159 panic("Atomic CPU doesn't expect recvTimingResp!\n");
165 panic("Atomic CPU doesn't expect recvRetry!\n");
170 class AtomicCPUDPort : public AtomicCPUPort
175 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu)
176 : AtomicCPUPort(_name, _cpu), cpu(_cpu)
178 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
181 bool isSnooping() const { return true; }
187 virtual Tick recvAtomicSnoop(PacketPtr pkt);
188 virtual void recvFunctionalSnoop(PacketPtr pkt);
192 AtomicCPUPort icachePort;
193 AtomicCPUDPort dcachePort;
197 Request data_read_req;
198 Request data_write_req;
204 * Profile basic blocks for SimPoints.
205 * Called at every macro inst to increment basic block inst counts and
206 * to profile block if end of block.
208 void profileSimPoint();
210 /** Data structures for SimPoints BBV generation
214 /** Whether SimPoint BBV profiling is enabled */
216 /** SimPoint profiling interval size in instructions */
217 const uint64_t intervalSize;
219 /** Inst count in current basic block */
220 uint64_t intervalCount;
221 /** Excess inst count from previous interval*/
222 uint64_t intervalDrift;
223 /** Pointer to SimPoint BBV output stream */
224 std::ostream *simpointStream;
226 /** Basic Block information */
230 /** Num of static insts in BB */
232 /** Accumulated dynamic inst count executed by BB */
236 /** Hash table containing all previously seen basic blocks */
237 m5::hash_map<BasicBlockRange, BBInfo> bbMap;
238 /** Currently executing basic block */
239 BasicBlockRange currentBBV;
240 /** inst count in current basic block */
241 uint64_t currentBBVInstCount;
244 * End of data structures for SimPoints BBV generation
249 /** Return a reference to the data port. */
250 virtual MasterPort &getDataPort() { return dcachePort; }
252 /** Return a reference to the instruction port. */
253 virtual MasterPort &getInstPort() { return icachePort; }
257 unsigned int drain(DrainManager *drain_manager);
261 void takeOverFrom(BaseCPU *oldCPU);
263 void verifyMemoryMode() const;
265 virtual void activateContext(ThreadID thread_num, Cycles delay);
266 virtual void suspendContext(ThreadID thread_num);
268 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
270 Fault writeMem(uint8_t *data, unsigned size,
271 Addr addr, unsigned flags, uint64_t *res);
274 * Print state of address in memory system via PrintReq (for
277 void printAddr(Addr a);
280 #endif // __CPU_SIMPLE_ATOMIC_HH__