2 * Copyright (c) 2012 ARM Limited
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14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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40 * Authors: Steve Reinhardt
43 #ifndef __CPU_SIMPLE_ATOMIC_HH__
44 #define __CPU_SIMPLE_ATOMIC_HH__
46 #include "cpu/simple/base.hh"
47 #include "params/AtomicSimpleCPU.hh"
49 class AtomicSimpleCPU : public BaseSimpleCPU
53 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
54 virtual ~AtomicSimpleCPU();
60 struct TickEvent : public Event
64 TickEvent(AtomicSimpleCPU *c);
66 const char *description() const;
73 const bool simulate_data_stalls;
74 const bool simulate_inst_stalls;
76 // main simulation loop (one cycle)
80 * An AtomicCPUPort overrides the default behaviour of the
81 * recvAtomic and ignores the packet instead of panicking.
83 class AtomicCPUPort : public CpuPort
88 AtomicCPUPort(const std::string &_name, BaseCPU* _cpu)
89 : CpuPort(_name, _cpu)
94 virtual Tick recvAtomic(PacketPtr pkt)
96 // Snooping a coherence request, just return
102 AtomicCPUPort icachePort;
103 AtomicCPUPort dcachePort;
107 Request data_read_req;
108 Request data_write_req;
115 /** Return a reference to the data port. */
116 virtual CpuPort &getDataPort() { return dcachePort; }
118 /** Return a reference to the instruction port. */
119 virtual CpuPort &getInstPort() { return icachePort; }
123 virtual void serialize(std::ostream &os);
124 virtual void unserialize(Checkpoint *cp, const std::string §ion);
125 virtual void resume();
128 void takeOverFrom(BaseCPU *oldCPU);
130 virtual void activateContext(ThreadID thread_num, int delay);
131 virtual void suspendContext(ThreadID thread_num);
133 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
135 Fault writeMem(uint8_t *data, unsigned size,
136 Addr addr, unsigned flags, uint64_t *res);
139 * Print state of address in memory system via PrintReq (for
142 void printAddr(Addr a);
145 #endif // __CPU_SIMPLE_ATOMIC_HH__