2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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28 * Authors: Steve Reinhardt
31 #ifndef __CPU_SIMPLE_ATOMIC_HH__
32 #define __CPU_SIMPLE_ATOMIC_HH__
34 #include "cpu/simple/base.hh"
36 class AtomicSimpleCPU : public BaseSimpleCPU
40 struct Params : public BaseSimpleCPU::Params {
45 AtomicSimpleCPU(Params *params);
46 virtual ~AtomicSimpleCPU();
61 Status status() const { return _status; }
65 struct TickEvent : public Event
69 TickEvent(AtomicSimpleCPU *c);
71 const char *description();
77 const bool simulate_stalls;
79 // main simulation loop (one cycle)
82 class CpuPort : public Port
86 CpuPort(const std::string &_name, AtomicSimpleCPU *_cpu)
87 : Port(_name, _cpu), cpu(_cpu)
96 virtual bool recvTiming(PacketPtr pkt);
98 virtual Tick recvAtomic(PacketPtr pkt);
100 virtual void recvFunctional(PacketPtr pkt);
102 virtual void recvStatusChange(Status status);
104 virtual void recvRetry();
106 virtual void getDeviceAddressRanges(AddrRangeList &resp,
107 AddrRangeList &snoop)
108 { resp.clear(); snoop.clear(); snoop.push_back(RangeSize(0,0)); }
113 class DcachePort : public CpuPort
116 DcachePort(const std::string &_name, AtomicSimpleCPU *_cpu)
117 : CpuPort(_name, _cpu)
120 virtual void setPeer(Port *port);
122 DcachePort dcachePort;
125 PacketPtr ifetch_pkt;
126 Request *data_read_req;
127 PacketPtr data_read_pkt;
128 Request *data_write_req;
129 PacketPtr data_write_pkt;
130 PacketPtr data_swap_pkt;
137 virtual Port *getPort(const std::string &if_name, int idx = -1);
139 virtual void serialize(std::ostream &os);
140 virtual void unserialize(Checkpoint *cp, const std::string §ion);
141 virtual void resume();
144 void takeOverFrom(BaseCPU *oldCPU);
146 virtual void activateContext(int thread_num, int delay);
147 virtual void suspendContext(int thread_num);
150 Fault read(Addr addr, T &data, unsigned flags);
153 Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
156 #endif // __CPU_SIMPLE_ATOMIC_HH__