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40 * Authors: Steve Reinhardt
43 #ifndef __CPU_SIMPLE_ATOMIC_HH__
44 #define __CPU_SIMPLE_ATOMIC_HH__
46 #include "cpu/simple/base.hh"
47 #include "params/AtomicSimpleCPU.hh"
48 #include "sim/probe/probe.hh"
50 class AtomicSimpleCPU : public BaseSimpleCPU
54 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
55 virtual ~AtomicSimpleCPU();
61 struct TickEvent : public Event
65 TickEvent(AtomicSimpleCPU *c);
67 const char *description() const;
74 const bool simulate_data_stalls;
75 const bool simulate_inst_stalls;
78 * Drain manager to use when signaling drain completion
80 * This pointer is non-NULL when draining and NULL otherwise.
82 DrainManager *drain_manager;
84 // main simulation loop (one cycle)
88 * Check if a system is in a drained state.
90 * We need to drain if:
92 * <li>We are in the middle of a microcode sequence as some CPUs
93 * (e.g., HW accelerated CPUs) can't be started in the middle
94 * of a gem5 microcode sequence.
96 * <li>The CPU is in a LLSC region. This shouldn't normally happen
97 * as these are executed atomically within a single tick()
98 * call. The only way this can happen at the moment is if
99 * there is an event in the PC event queue that affects the
100 * CPU state while it is in an LLSC region.
102 * <li>Stay at PC is true.
106 return microPC() == 0 &&
112 * Try to complete a drain request.
114 * @returns true if the CPU is drained, false otherwise.
116 bool tryCompleteDrain();
119 * An AtomicCPUPort overrides the default behaviour of the
120 * recvAtomicSnoop and ignores the packet instead of panicking. It
121 * also provides an implementation for the purely virtual timing
122 * functions and panics on either of these.
124 class AtomicCPUPort : public MasterPort
129 AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
130 : MasterPort(_name, _cpu)
134 virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
136 bool recvTimingResp(PacketPtr pkt)
138 panic("Atomic CPU doesn't expect recvTimingResp!\n");
144 panic("Atomic CPU doesn't expect recvRetry!\n");
149 class AtomicCPUDPort : public AtomicCPUPort
154 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu)
155 : AtomicCPUPort(_name, _cpu), cpu(_cpu)
157 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
160 bool isSnooping() const { return true; }
166 virtual Tick recvAtomicSnoop(PacketPtr pkt);
167 virtual void recvFunctionalSnoop(PacketPtr pkt);
171 AtomicCPUPort icachePort;
172 AtomicCPUDPort dcachePort;
176 Request data_read_req;
177 Request data_write_req;
183 ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit;
187 /** Return a reference to the data port. */
188 virtual MasterPort &getDataPort() { return dcachePort; }
190 /** Return a reference to the instruction port. */
191 virtual MasterPort &getInstPort() { return icachePort; }
195 unsigned int drain(DrainManager *drain_manager);
199 void takeOverFrom(BaseCPU *oldCPU);
201 void verifyMemoryMode() const;
203 virtual void activateContext(ThreadID thread_num);
204 virtual void suspendContext(ThreadID thread_num);
206 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
208 Fault writeMem(uint8_t *data, unsigned size,
209 Addr addr, unsigned flags, uint64_t *res);
211 virtual void regProbePoints();
214 * Print state of address in memory system via PrintReq (for
217 void printAddr(Addr a);
220 #endif // __CPU_SIMPLE_ATOMIC_HH__