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40 * Authors: Steve Reinhardt
43 #ifndef __CPU_SIMPLE_ATOMIC_HH__
44 #define __CPU_SIMPLE_ATOMIC_HH__
46 #include "cpu/simple/base.hh"
47 #include "cpu/simple/exec_context.hh"
48 #include "params/AtomicSimpleCPU.hh"
49 #include "sim/probe/probe.hh"
51 class AtomicSimpleCPU : public BaseSimpleCPU
55 AtomicSimpleCPU(AtomicSimpleCPUParams *params);
56 virtual ~AtomicSimpleCPU();
62 struct TickEvent : public Event
66 TickEvent(AtomicSimpleCPU *c);
68 const char *description() const;
75 const bool simulate_data_stalls;
76 const bool simulate_inst_stalls;
78 // main simulation loop (one cycle)
82 * Check if a system is in a drained state.
84 * We need to drain if:
86 * <li>We are in the middle of a microcode sequence as some CPUs
87 * (e.g., HW accelerated CPUs) can't be started in the middle
88 * of a gem5 microcode sequence.
90 * <li>The CPU is in a LLSC region. This shouldn't normally happen
91 * as these are executed atomically within a single tick()
92 * call. The only way this can happen at the moment is if
93 * there is an event in the PC event queue that affects the
94 * CPU state while it is in an LLSC region.
96 * <li>Stay at PC is true.
100 SimpleExecContext &t_info = *threadInfo[curThread];
102 return t_info.thread->microPC() == 0 &&
108 * Try to complete a drain request.
110 * @returns true if the CPU is drained, false otherwise.
112 bool tryCompleteDrain();
115 * An AtomicCPUPort overrides the default behaviour of the
116 * recvAtomicSnoop and ignores the packet instead of panicking. It
117 * also provides an implementation for the purely virtual timing
118 * functions and panics on either of these.
120 class AtomicCPUPort : public MasterPort
125 AtomicCPUPort(const std::string &_name, BaseSimpleCPU* _cpu)
126 : MasterPort(_name, _cpu)
130 virtual Tick recvAtomicSnoop(PacketPtr pkt) { return 0; }
132 bool recvTimingResp(PacketPtr pkt)
134 panic("Atomic CPU doesn't expect recvTimingResp!\n");
140 panic("Atomic CPU doesn't expect recvRetry!\n");
145 class AtomicCPUDPort : public AtomicCPUPort
150 AtomicCPUDPort(const std::string &_name, BaseSimpleCPU* _cpu)
151 : AtomicCPUPort(_name, _cpu), cpu(_cpu)
153 cacheBlockMask = ~(cpu->cacheLineSize() - 1);
156 bool isSnooping() const { return true; }
162 virtual Tick recvAtomicSnoop(PacketPtr pkt);
163 virtual void recvFunctionalSnoop(PacketPtr pkt);
167 AtomicCPUPort icachePort;
168 AtomicCPUDPort dcachePort;
172 Request data_read_req;
173 Request data_write_req;
179 ProbePointArg<std::pair<SimpleThread*, const StaticInstPtr>> *ppCommit;
183 /** Return a reference to the data port. */
184 virtual MasterPort &getDataPort() { return dcachePort; }
186 /** Return a reference to the instruction port. */
187 virtual MasterPort &getInstPort() { return icachePort; }
189 /** Perform snoop for other cpu-local thread contexts. */
190 void threadSnoop(PacketPtr pkt, ThreadID sender);
194 DrainState drain() M5_ATTR_OVERRIDE;
195 void drainResume() M5_ATTR_OVERRIDE;
198 void takeOverFrom(BaseCPU *oldCPU);
200 void verifyMemoryMode() const;
202 virtual void activateContext(ThreadID thread_num);
203 virtual void suspendContext(ThreadID thread_num);
205 Fault readMem(Addr addr, uint8_t *data, unsigned size, unsigned flags);
207 Fault writeMem(uint8_t *data, unsigned size,
208 Addr addr, unsigned flags, uint64_t *res);
210 virtual void regProbePoints();
213 * Print state of address in memory system via PrintReq (for
216 void printAddr(Addr a);
219 #endif // __CPU_SIMPLE_ATOMIC_HH__