2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
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14 * this software without specific prior written permission.
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29 #include "arch/utility.hh"
30 #include "base/cprintf.hh"
31 #include "base/inifile.hh"
32 #include "base/loader/symtab.hh"
33 #include "base/misc.hh"
34 #include "base/pollevent.hh"
35 #include "base/range.hh"
36 #include "base/stats/events.hh"
37 #include "base/trace.hh"
38 #include "cpu/base.hh"
39 #include "cpu/cpu_exec_context.hh"
40 #include "cpu/exec_context.hh"
41 #include "cpu/exetrace.hh"
42 #include "cpu/profile.hh"
43 #include "cpu/sampler/sampler.hh"
44 #include "cpu/simple/base.hh"
46 #include "cpu/static_inst.hh"
47 #include "kern/kernel_stats.hh"
48 #include "mem/packet_impl.hh"
49 #include "sim/byteswap.hh"
50 #include "sim/builder.hh"
51 #include "sim/debug.hh"
52 #include "sim/host.hh"
53 #include "sim/sim_events.hh"
54 #include "sim/sim_object.hh"
55 #include "sim/stats.hh"
58 #include "base/remote_gdb.hh"
59 #include "sim/system.hh"
60 #include "arch/tlb.hh"
61 #include "arch/stacktrace.hh"
62 #include "arch/vtophys.hh"
64 #include "mem/mem_object.hh"
68 using namespace TheISA
;
70 BaseSimpleCPU::BaseSimpleCPU(Params
*p
)
71 : BaseCPU(p
), mem(p
->mem
), cpuXC(NULL
)
74 cpuXC
= new CPUExecContext(this, 0, p
->system
, p
->itb
, p
->dtb
);
76 cpuXC
= new CPUExecContext(this, /* thread_num */ 0, p
->process
,
78 #endif // !FULL_SYSTEM
80 xcProxy
= cpuXC
->getProxy();
89 execContexts
.push_back(xcProxy
);
92 BaseSimpleCPU::~BaseSimpleCPU()
97 BaseSimpleCPU::deallocateContext(int thread_num
)
99 // for now, these are equivalent
100 suspendContext(thread_num
);
105 BaseSimpleCPU::haltContext(int thread_num
)
107 // for now, these are equivalent
108 suspendContext(thread_num
);
113 BaseSimpleCPU::regStats()
115 using namespace Stats
;
120 .name(name() + ".num_insts")
121 .desc("Number of instructions executed")
125 .name(name() + ".num_refs")
126 .desc("Number of memory references")
130 .name(name() + ".not_idle_fraction")
131 .desc("Percentage of non-idle cycles")
135 .name(name() + ".idle_fraction")
136 .desc("Percentage of idle cycles")
140 .name(name() + ".icache_stall_cycles")
141 .desc("ICache total stall cycles")
142 .prereq(icacheStallCycles
)
146 .name(name() + ".dcache_stall_cycles")
147 .desc("DCache total stall cycles")
148 .prereq(dcacheStallCycles
)
152 .name(name() + ".icache_retry_cycles")
153 .desc("ICache total retry cycles")
154 .prereq(icacheRetryCycles
)
158 .name(name() + ".dcache_retry_cycles")
159 .desc("DCache total retry cycles")
160 .prereq(dcacheRetryCycles
)
163 idleFraction
= constant(1.0) - notIdleFraction
;
167 BaseSimpleCPU::resetStats()
169 startNumInst
= numInst
;
170 // notIdleFraction = (_status != Idle);
174 BaseSimpleCPU::serialize(ostream
&os
)
176 BaseCPU::serialize(os
);
177 SERIALIZE_SCALAR(inst
);
178 nameOut(os
, csprintf("%s.xc", name()));
179 cpuXC
->serialize(os
);
183 BaseSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
185 BaseCPU::unserialize(cp
, section
);
186 UNSERIALIZE_SCALAR(inst
);
187 cpuXC
->unserialize(cp
, csprintf("%s.xc", section
));
191 change_thread_state(int thread_number
, int activate
, int priority
)
196 BaseSimpleCPU::copySrcTranslate(Addr src
)
199 static bool no_warn
= true;
200 int blk_size
= (dcacheInterface
) ? dcacheInterface
->getBlockSize() : 64;
201 // Only support block sizes of 64 atm.
202 assert(blk_size
== 64);
203 int offset
= src
& (blk_size
- 1);
205 // Make sure block doesn't span page
207 (src
& PageMask
) != ((src
+ blk_size
) & PageMask
) &&
208 (src
>> 40) != 0xfffffc) {
209 warn("Copied block source spans pages %x.", src
);
213 memReq
->reset(src
& ~(blk_size
- 1), blk_size
);
215 // translate to physical address
216 Fault fault
= cpuXC
->translateDataReadReq(req
);
218 if (fault
== NoFault
) {
219 cpuXC
->copySrcAddr
= src
;
220 cpuXC
->copySrcPhysAddr
= memReq
->paddr
+ offset
;
222 assert(!fault
->isAlignmentFault());
224 cpuXC
->copySrcAddr
= 0;
225 cpuXC
->copySrcPhysAddr
= 0;
234 BaseSimpleCPU::copy(Addr dest
)
237 static bool no_warn
= true;
238 int blk_size
= (dcacheInterface
) ? dcacheInterface
->getBlockSize() : 64;
239 // Only support block sizes of 64 atm.
240 assert(blk_size
== 64);
241 uint8_t data
[blk_size
];
242 //assert(cpuXC->copySrcAddr);
243 int offset
= dest
& (blk_size
- 1);
245 // Make sure block doesn't span page
247 (dest
& PageMask
) != ((dest
+ blk_size
) & PageMask
) &&
248 (dest
>> 40) != 0xfffffc) {
250 warn("Copied block destination spans pages %x. ", dest
);
253 memReq
->reset(dest
& ~(blk_size
-1), blk_size
);
254 // translate to physical address
255 Fault fault
= cpuXC
->translateDataWriteReq(req
);
257 if (fault
== NoFault
) {
258 Addr dest_addr
= memReq
->paddr
+ offset
;
259 // Need to read straight from memory since we have more than 8 bytes.
260 memReq
->paddr
= cpuXC
->copySrcPhysAddr
;
261 cpuXC
->mem
->read(memReq
, data
);
262 memReq
->paddr
= dest_addr
;
263 cpuXC
->mem
->write(memReq
, data
);
264 if (dcacheInterface
) {
266 memReq
->completionEvent
= NULL
;
267 memReq
->paddr
= cpuXC
->copySrcPhysAddr
;
268 memReq
->dest
= dest_addr
;
270 memReq
->time
= curTick
;
271 memReq
->flags
&= ~INST_READ
;
272 dcacheInterface
->access(memReq
);
276 assert(!fault
->isAlignmentFault());
280 panic("copy not implemented");
287 BaseSimpleCPU::dbg_vtophys(Addr addr
)
289 return vtophys(xcProxy
, addr
);
291 #endif // FULL_SYSTEM
295 BaseSimpleCPU::post_interrupt(int int_num
, int index
)
297 BaseCPU::post_interrupt(int_num
, index
);
299 if (cpuXC
->status() == ExecContext::Suspended
) {
300 DPRINTF(IPI
,"Suspended Processor awoke\n");
304 #endif // FULL_SYSTEM
307 BaseSimpleCPU::checkForInterrupts()
310 if (checkInterrupts
&& check_interrupts() && !cpuXC
->inPalMode()) {
313 checkInterrupts
= false;
315 if (cpuXC
->readMiscReg(IPR_SIRR
)) {
316 for (int i
= INTLEVEL_SOFTWARE_MIN
;
317 i
< INTLEVEL_SOFTWARE_MAX
; i
++) {
318 if (cpuXC
->readMiscReg(IPR_SIRR
) & (ULL(1) << i
)) {
319 // See table 4-19 of 21164 hardware reference
320 ipl
= (i
- INTLEVEL_SOFTWARE_MIN
) + 1;
321 summary
|= (ULL(1) << i
);
326 uint64_t interrupts
= cpuXC
->cpu
->intr_status();
327 for (int i
= INTLEVEL_EXTERNAL_MIN
;
328 i
< INTLEVEL_EXTERNAL_MAX
; i
++) {
329 if (interrupts
& (ULL(1) << i
)) {
330 // See table 4-19 of 21164 hardware reference
332 summary
|= (ULL(1) << i
);
336 if (cpuXC
->readMiscReg(IPR_ASTRR
))
337 panic("asynchronous traps not implemented\n");
339 if (ipl
&& ipl
> cpuXC
->readMiscReg(IPR_IPLR
)) {
340 cpuXC
->setMiscReg(IPR_ISR
, summary
);
341 cpuXC
->setMiscReg(IPR_INTID
, ipl
);
343 Fault(new InterruptFault
)->invoke(xcProxy
);
345 DPRINTF(Flow
, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
346 cpuXC
->readMiscReg(IPR_IPLR
), ipl
, summary
);
354 BaseSimpleCPU::setupFetchPacket(Packet
*ifetch_pkt
)
356 // Try to fetch an instruction
358 // set up memory request for instruction fetch
360 DPRINTF(Fetch
,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",cpuXC
->readPC(),
361 cpuXC
->readNextPC(),cpuXC
->readNextNPC());
363 Request
*ifetch_req
= ifetch_pkt
->req
;
364 ifetch_req
->setVaddr(cpuXC
->readPC() & ~3);
365 ifetch_req
->setTime(curTick
);
367 ifetch_req
->setFlags((cpuXC
->readPC() & 1) ? PHYSICAL
: 0);
369 ifetch_req
->setFlags(0);
372 Fault fault
= cpuXC
->translateInstReq(ifetch_req
);
374 if (fault
== NoFault
) {
375 ifetch_pkt
->addr
= ifetch_req
->getPaddr();
383 BaseSimpleCPU::preExecute()
385 // maintain $r0 semantics
386 cpuXC
->setIntReg(ZeroReg
, 0);
387 #if THE_ISA == ALPHA_ISA
388 cpuXC
->setFloatReg(ZeroReg
, 0.0);
391 // keep an instruction count
395 cpuXC
->func_exe_inst
++;
397 // check for instruction-count-based events
398 comInstEventQueue
[0]->serviceEvents(numInst
);
400 // decode the instruction
402 curStaticInst
= StaticInst::decode(makeExtMI(inst
, cpuXC
->readPC()));
404 traceData
= Trace::getInstRecord(curTick
, xcProxy
, this, curStaticInst
,
407 DPRINTF(Decode
,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
408 curStaticInst
->getName(), curStaticInst
->getOpcode(),
409 curStaticInst
->machInst
);
412 cpuXC
->setInst(inst
);
413 #endif // FULL_SYSTEM
417 BaseSimpleCPU::postExecute()
420 if (system
->kernelBinning
->fnbin
) {
422 system
->kernelBinning
->execute(xcProxy
, inst
);
425 if (cpuXC
->profile
) {
427 (cpuXC
->readMiscReg(AlphaISA::IPR_DTB_CM
) & 0x18) != 0;
428 cpuXC
->profilePC
= usermode
? 1 : cpuXC
->readPC();
429 ProfileNode
*node
= cpuXC
->profile
->consume(xcProxy
, inst
);
431 cpuXC
->profileNode
= node
;
435 if (curStaticInst
->isMemRef()) {
439 if (curStaticInst
->isLoad()) {
441 comLoadEventQueue
[0]->serviceEvents(numLoad
);
444 traceFunctions(cpuXC
->readPC());
449 BaseSimpleCPU::advancePC(Fault fault
)
451 if (fault
!= NoFault
) {
453 fault
->invoke(xcProxy
);
454 #else // !FULL_SYSTEM
455 fatal("fault (%s) detected @ PC %08p", fault
->name(), cpuXC
->readPC());
456 #endif // FULL_SYSTEM
459 // go to the next instruction
460 cpuXC
->setPC(cpuXC
->readNextPC());
461 #if THE_ISA == ALPHA_ISA
462 cpuXC
->setNextPC(cpuXC
->readNextPC() + sizeof(MachInst
));
464 cpuXC
->setNextPC(cpuXC
->readNextNPC());
465 cpuXC
->setNextNPC(cpuXC
->readNextNPC() + sizeof(MachInst
));
473 oldpc
= cpuXC
->readPC();
474 system
->pcEventQueue
.service(xcProxy
);
475 } while (oldpc
!= cpuXC
->readPC());