2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * Authors: Steve Reinhardt
31 #include "arch/utility.hh"
32 #include "arch/faults.hh"
33 #include "base/cprintf.hh"
34 #include "base/inifile.hh"
35 #include "base/loader/symtab.hh"
36 #include "base/misc.hh"
37 #include "base/pollevent.hh"
38 #include "base/range.hh"
39 #include "base/stats/events.hh"
40 #include "base/trace.hh"
41 #include "cpu/base.hh"
42 #include "cpu/exetrace.hh"
43 #include "cpu/profile.hh"
44 #include "cpu/simple/base.hh"
45 #include "cpu/simple_thread.hh"
47 #include "cpu/static_inst.hh"
48 #include "cpu/thread_context.hh"
49 #include "mem/packet.hh"
50 #include "sim/builder.hh"
51 #include "sim/byteswap.hh"
52 #include "sim/debug.hh"
53 #include "sim/host.hh"
54 #include "sim/sim_events.hh"
55 #include "sim/sim_object.hh"
56 #include "sim/stats.hh"
57 #include "sim/system.hh"
60 #include "arch/kernel_stats.hh"
61 #include "arch/stacktrace.hh"
62 #include "arch/tlb.hh"
63 #include "arch/vtophys.hh"
64 #include "base/remote_gdb.hh"
66 #include "mem/mem_object.hh"
70 using namespace TheISA
;
72 BaseSimpleCPU::BaseSimpleCPU(Params
*p
)
73 : BaseCPU(p
), thread(NULL
)
76 thread
= new SimpleThread(this, 0, p
->system
, p
->itb
, p
->dtb
);
78 thread
= new SimpleThread(this, /* thread_num */ 0, p
->process
,
80 #endif // !FULL_SYSTEM
82 thread
->setStatus(ThreadContext::Suspended
);
93 threadContexts
.push_back(tc
);
96 BaseSimpleCPU::~BaseSimpleCPU()
101 BaseSimpleCPU::deallocateContext(int thread_num
)
103 // for now, these are equivalent
104 suspendContext(thread_num
);
109 BaseSimpleCPU::haltContext(int thread_num
)
111 // for now, these are equivalent
112 suspendContext(thread_num
);
117 BaseSimpleCPU::regStats()
119 using namespace Stats
;
124 .name(name() + ".num_insts")
125 .desc("Number of instructions executed")
129 .name(name() + ".num_refs")
130 .desc("Number of memory references")
134 .name(name() + ".not_idle_fraction")
135 .desc("Percentage of non-idle cycles")
139 .name(name() + ".idle_fraction")
140 .desc("Percentage of idle cycles")
144 .name(name() + ".icache_stall_cycles")
145 .desc("ICache total stall cycles")
146 .prereq(icacheStallCycles
)
150 .name(name() + ".dcache_stall_cycles")
151 .desc("DCache total stall cycles")
152 .prereq(dcacheStallCycles
)
156 .name(name() + ".icache_retry_cycles")
157 .desc("ICache total retry cycles")
158 .prereq(icacheRetryCycles
)
162 .name(name() + ".dcache_retry_cycles")
163 .desc("DCache total retry cycles")
164 .prereq(dcacheRetryCycles
)
167 idleFraction
= constant(1.0) - notIdleFraction
;
171 BaseSimpleCPU::resetStats()
173 // startNumInst = numInst;
174 // notIdleFraction = (_status != Idle);
178 BaseSimpleCPU::serialize(ostream
&os
)
180 BaseCPU::serialize(os
);
181 // SERIALIZE_SCALAR(inst);
182 nameOut(os
, csprintf("%s.xc.0", name()));
183 thread
->serialize(os
);
187 BaseSimpleCPU::unserialize(Checkpoint
*cp
, const string
§ion
)
189 BaseCPU::unserialize(cp
, section
);
190 // UNSERIALIZE_SCALAR(inst);
191 thread
->unserialize(cp
, csprintf("%s.xc.0", section
));
195 change_thread_state(int thread_number
, int activate
, int priority
)
200 BaseSimpleCPU::copySrcTranslate(Addr src
)
203 static bool no_warn
= true;
204 int blk_size
= (dcacheInterface
) ? dcacheInterface
->getBlockSize() : 64;
205 // Only support block sizes of 64 atm.
206 assert(blk_size
== 64);
207 int offset
= src
& (blk_size
- 1);
209 // Make sure block doesn't span page
211 (src
& PageMask
) != ((src
+ blk_size
) & PageMask
) &&
212 (src
>> 40) != 0xfffffc) {
213 warn("Copied block source spans pages %x.", src
);
217 memReq
->reset(src
& ~(blk_size
- 1), blk_size
);
219 // translate to physical address
220 Fault fault
= thread
->translateDataReadReq(req
);
222 if (fault
== NoFault
) {
223 thread
->copySrcAddr
= src
;
224 thread
->copySrcPhysAddr
= memReq
->paddr
+ offset
;
226 assert(!fault
->isAlignmentFault());
228 thread
->copySrcAddr
= 0;
229 thread
->copySrcPhysAddr
= 0;
238 BaseSimpleCPU::copy(Addr dest
)
241 static bool no_warn
= true;
242 int blk_size
= (dcacheInterface
) ? dcacheInterface
->getBlockSize() : 64;
243 // Only support block sizes of 64 atm.
244 assert(blk_size
== 64);
245 uint8_t data
[blk_size
];
246 //assert(thread->copySrcAddr);
247 int offset
= dest
& (blk_size
- 1);
249 // Make sure block doesn't span page
251 (dest
& PageMask
) != ((dest
+ blk_size
) & PageMask
) &&
252 (dest
>> 40) != 0xfffffc) {
254 warn("Copied block destination spans pages %x. ", dest
);
257 memReq
->reset(dest
& ~(blk_size
-1), blk_size
);
258 // translate to physical address
259 Fault fault
= thread
->translateDataWriteReq(req
);
261 if (fault
== NoFault
) {
262 Addr dest_addr
= memReq
->paddr
+ offset
;
263 // Need to read straight from memory since we have more than 8 bytes.
264 memReq
->paddr
= thread
->copySrcPhysAddr
;
265 thread
->mem
->read(memReq
, data
);
266 memReq
->paddr
= dest_addr
;
267 thread
->mem
->write(memReq
, data
);
268 if (dcacheInterface
) {
270 memReq
->completionEvent
= NULL
;
271 memReq
->paddr
= thread
->copySrcPhysAddr
;
272 memReq
->dest
= dest_addr
;
274 memReq
->time
= curTick
;
275 memReq
->flags
&= ~INST_READ
;
276 dcacheInterface
->access(memReq
);
280 assert(!fault
->isAlignmentFault());
284 panic("copy not implemented");
291 BaseSimpleCPU::dbg_vtophys(Addr addr
)
293 return vtophys(tc
, addr
);
295 #endif // FULL_SYSTEM
299 BaseSimpleCPU::post_interrupt(int int_num
, int index
)
301 BaseCPU::post_interrupt(int_num
, index
);
303 if (thread
->status() == ThreadContext::Suspended
) {
304 DPRINTF(IPI
,"Suspended Processor awoke\n");
308 #endif // FULL_SYSTEM
311 BaseSimpleCPU::checkForInterrupts()
314 if (check_interrupts(tc
)) {
315 Fault interrupt
= interrupts
.getInterrupt(tc
);
317 if (interrupt
!= NoFault
) {
318 interrupts
.updateIntrInfo(tc
);
319 interrupt
->invoke(tc
);
327 BaseSimpleCPU::setupFetchRequest(Request
*req
)
329 // set up memory request for instruction fetch
330 #if ISA_HAS_DELAY_SLOT
331 DPRINTF(Fetch
,"Fetch: PC:%08p NPC:%08p NNPC:%08p\n",thread
->readPC(),
332 thread
->readNextPC(),thread
->readNextNPC());
334 DPRINTF(Fetch
,"Fetch: PC:%08p NPC:%08p",thread
->readPC(),
335 thread
->readNextPC());
338 req
->setVirt(0, thread
->readPC() & ~3, sizeof(MachInst
),
339 (FULL_SYSTEM
&& (thread
->readPC() & 1)) ? PHYSICAL
: 0,
342 Fault fault
= thread
->translateInstReq(req
);
349 BaseSimpleCPU::preExecute()
351 // maintain $r0 semantics
352 thread
->setIntReg(ZeroReg
, 0);
353 #if THE_ISA == ALPHA_ISA
354 thread
->setFloatReg(ZeroReg
, 0.0);
357 // keep an instruction count
361 thread
->funcExeInst
++;
363 // check for instruction-count-based events
364 comInstEventQueue
[0]->serviceEvents(numInst
);
366 // decode the instruction
368 //If we're not in the middle of a macro instruction
369 if (!curMacroStaticInst
) {
370 #if THE_ISA == ALPHA_ISA
371 StaticInstPtr instPtr
= StaticInst::decode(makeExtMI(inst
, thread
->readPC()));
372 #elif THE_ISA == SPARC_ISA
373 StaticInstPtr instPtr
= StaticInst::decode(makeExtMI(inst
, thread
->getTC()));
374 #elif THE_ISA == MIPS_ISA
375 //Mips doesn't do anything in it's MakeExtMI function right now,
376 //so it won't be called.
377 StaticInstPtr instPtr
= StaticInst::decode(inst
);
379 if (instPtr
->isMacroOp()) {
380 curMacroStaticInst
= instPtr
;
381 curStaticInst
= curMacroStaticInst
->
382 fetchMicroOp(thread
->readMicroPC());
384 curStaticInst
= instPtr
;
387 //Read the next micro op from the macro op
388 curStaticInst
= curMacroStaticInst
->
389 fetchMicroOp(thread
->readMicroPC());
393 traceData
= Trace::getInstRecord(curTick
, tc
, curStaticInst
,
396 DPRINTF(Decode
,"Decode: Decoded %s instruction (opcode: 0x%x): 0x%x\n",
397 curStaticInst
->getName(), curStaticInst
->getOpcode(),
398 curStaticInst
->machInst
);
401 thread
->setInst(inst
);
402 #endif // FULL_SYSTEM
406 BaseSimpleCPU::postExecute()
409 if (thread
->profile
) {
410 bool usermode
= TheISA::inUserMode(tc
);
411 thread
->profilePC
= usermode
? 1 : thread
->readPC();
412 ProfileNode
*node
= thread
->profile
->consume(tc
, inst
);
414 thread
->profileNode
= node
;
418 if (curStaticInst
->isMemRef()) {
422 if (curStaticInst
->isLoad()) {
424 comLoadEventQueue
[0]->serviceEvents(numLoad
);
427 traceFunctions(thread
->readPC());
438 BaseSimpleCPU::advancePC(Fault fault
)
440 if (fault
!= NoFault
) {
441 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
443 thread
->setMicroPC(0);
444 thread
->setNextMicroPC(1);
446 //If we're at the last micro op for this instruction
447 if (curStaticInst
->isLastMicroOp()) {
448 //We should be working with a macro op
449 assert(curMacroStaticInst
);
450 //Close out this macro op, and clean up the
452 curMacroStaticInst
= StaticInst::nullStaticInstPtr
;
453 thread
->setMicroPC(0);
454 thread
->setNextMicroPC(1);
456 //If we're still in a macro op
457 if (curMacroStaticInst
) {
458 //Advance the micro pc
459 thread
->setMicroPC(thread
->readNextMicroPC());
460 //Advance the "next" micro pc. Note that there are no delay
461 //slots, and micro ops are "word" addressed.
462 thread
->setNextMicroPC(thread
->readNextMicroPC() + 1);
464 // go to the next instruction
465 thread
->setPC(thread
->readNextPC());
466 #if ISA_HAS_DELAY_SLOT
467 thread
->setNextPC(thread
->readNextNPC());
468 thread
->setNextNPC(thread
->readNextNPC() + sizeof(MachInst
));
469 assert(thread
->readNextPC() != thread
->readNextNPC());
471 thread
->setNextPC(thread
->readNextPC() + sizeof(MachInst
));
479 oldpc
= thread
->readPC();
480 system
->pcEventQueue
.service(tc
);
481 } while (oldpc
!= thread
->readPC());